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Chapter 15
Power Management Controller (PMC)
15.1 Introduction
The power management controller (PMC) contains the internal voltage regulator, power
on reset (POR), and low voltage detect system (LVD).
See
AN4503: Power Management for Kinetis MCUs
PMC.
15.2 Features
A list of included PMC features can be found here.
• Internal voltage regulator
• Active POR providing brown-out detect
• Low-voltage detect supporting two low-voltage trip points with four warning levels
per trip point
15.3 Low-voltage detect (LVD) system
This device includes a system to guard against low-voltage conditions. This protects
memory contents and controls MCU system states during supply voltage variations.
The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a
user-selectable trip voltage: high (V
LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes.
Two flags are available to indicate the status of the low-voltage detect system:
• The Low Voltage Detect Flag in the Low Voltage Status and Control 1 Register
(LVDSC1[LVDF]) operates in a level sensitive manner. LVDSC1[LVDF] is set
Freescale Semiconductor, Inc.
) or low (V
LVDH
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
for further details on using the
). The trip voltage is selected by
LVDL
241
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