System Clock Gating Control Register 6 (Sim_Scgc6) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition

12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)

Address: 4004_7000h base + 103Ch offset = 4004_803Ch
Bit 31 30 29
0
R
RTC
W
Reset
0 0 0
Bit 15 14 13
R
I2S
W
Reset
0 0 0
Field
31 DAC0 Clock Gate Control
DAC0
This bit controls the clock gate to the DAC0 module.
0 Clock disabled
1 Clock enabled
30 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
29 RTC Access Control
RTC
Controls software access and interrupts to the RTC module.
0 Access and interrupts disabled
1 Access and interrupts enabled
28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27 ADC0 Clock Gate Control
ADC0
Controls the clock gate to the ADC0 module.
0 Clock disabled
1 Clock enabled
26 TPM2 Clock Gate Control
TPM2
Controls the clock gate to the TPM2 module.
0 Clock disabled
1 Clock enabled
160
28 27 26 25
0
0 0 0 0
12 11 10 9
0 0 0 0
SIM_SCGC6 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24 23 22 21
0
PIT
0 0 0 0
8 7 6 5
0
0 0 0 0
Description
20 19 18 17
0 0
0 0 0 0
4 3 2 1
0 0 0 0
Freescale Semiconductor, Inc.
16
0
0
FTF
1