Dma Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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cycle, and then a logic 0 (the asserted level) during the next cycle. A rising edge is

detected when the input is seen as a logic 0 during one module clock cycle and then a

logic 1 during the next cycle.

38.7.1.2 Clearing RXEDGIF interrupt request

Writing a logic 1 to S2[RXEDGIF] immediately clears the RXEDGIF interrupt request

even if the RxD input remains asserted. S2[RXEDGIF] remains set if another active edge

is detected on RxD while attempting to clear S2[RXEDGIF] by writing a 1 to it.

38.7.1.3 Exit from low-power modes

The receive input active edge detect circuit is still active on low power modes (Wait and

Stop). An active edge on the receive input brings the CPU out of low power mode if the

interrupt is not masked (S2[RXEDGIF] = 1).

38.8 DMA operation

In the transmitter, S1[TDRE] can be configured to assert a DMA transfer request. In the

receiver, S1[RDRF], can be configured to assert a DMA transfer request. The following

table shows the configuration field settings required to configure each flag for DMA

When a flag is configured for a DMA request, its associated DMA request is asserted

when the flag is set. When S1[RDRF] is configured as a DMA request, the clearing

mechanism of reading S1, followed by reading D, does not clear the associated flag. The

DMA request remains asserted until an indication is received that the DMA transactions

are done. When this indication is received, the flag bit and the associated DMA request is

cleared. If the DMA operation failed to remove the situation that caused the DMA

request, another request is issued.

Freescale Semiconductor, Inc.

Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)

Table 38-15. DMA configuration

Request enable bit

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

DMA select bit