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NXP Semiconductors K53 Series Reference Manual

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K53 Sub-Family Reference Manual

Supports: MK53DN512ZCLQ10, MK53DN512ZCMD10,

MK53DX256ZCLQ10, MK53DX256ZCMD10

Document Number: K53P144M100SF2RM

Rev. 6, Nov 2011

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Page 1 K53 Sub-Family Reference Manual Supports: MK53DN512ZCLQ10, MK53DN512ZCMD10, MK53DX256ZCLQ10, MK53DX256ZCMD10 Document Number: K53P144M100SF2RM Rev. 6, Nov 2011...
Page 2 K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Contents Section Number Title Page Chapter 1 About This Document Overview..................................59 1.1.1 Purpose.................................59 1.1.2 Audience..............................59 Conventions..................................59 1.2.1 Numbering systems............................59 1.2.2 Typographic notation...........................60 1.2.3 Special terms..............................60 Chapter 2 Introduction Overview..................................61 K50 Family Introduction...............................61 Module Functional Categories............................61 2.3.1 ARM Cortex-M4 Core Modules........................63 2.3.2 System Modules............................63 2.3.3...
Page 4 Section Number Title Page Core modules................................71 3.2.1 ARM Cortex-M4 Core Configuration......................71 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration..............74 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration............80 3.2.4 JTAG Controller Configuration........................81 System modules................................82 3.3.1 SIM Configuration............................82 3.3.2 Mode Controller Configuration........................83 3.3.3 PMC Configuration............................83 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................84 3.3.5...
Page 5 Section Number Title Page 3.5.5 System Register File Configuration......................110 3.5.6 VBAT Register File Configuration......................111 3.5.7 EzPort Configuration...........................112 3.5.8 FlexBus Configuration..........................113 Security..................................116 3.6.1 CRC Configuration............................116 3.6.2 MMCAU Configuration..........................117 3.6.3 RNG Configuration............................118 K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 6 Section Number Title Page Analog...................................118 3.7.1 16-bit SAR ADC with PGA Configuration....................118 3.7.2 CMP Configuration............................126 3.7.3 12-bit DAC Configuration...........................128 3.7.4 Op-amp Configuration..........................129 3.7.5 TRIAMP Configuration..........................131 3.7.6 VREF Configuration............................132 Timers...................................133 3.8.1 PDB Configuration............................133 3.8.2 FlexTimer Configuration..........................137 3.8.3 PIT Configuration............................140 3.8.4 Low-power timer configuration........................141 3.8.5 CMT Configuration............................143 3.8.6...
Page 7 Section Number Title Page System memory map..............................169 4.2.1 Aliased bit-band regions..........................170 Flash Memory Map...............................171 4.3.1 Alternate Non-Volatile IRC User Trim Description..................172 SRAM memory map..............................173 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................173 4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map..................173 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map..................177 Private Peripheral Bus (PPB) memory map........................182 Chapter 5...
Page 8 Section Number Title Page 5.7.9 SDHC clocking............................194 5.7.10 I2S clocking..............................195 5.7.11 TSI clocking..............................195 Chapter 6 Reset and Boot Introduction...................................197 Reset....................................197 6.2.1 Power-on reset (POR)..........................198 6.2.2 System resets..............................198 6.2.3 Debug resets..............................201 Boot....................................203 6.3.1 Boot sources..............................203 6.3.2 Boot options..............................203 6.3.3 FOPT boot options............................203 6.3.4 Boot sequence..............................204 Chapter 7...
Page 9 Section Number Title Page 8.3.2 Security Interactions with EzPort........................216 8.3.3 Security Interactions with Debug.........................216 Chapter 9 Debug Introduction...................................219 9.1.1 References..............................221 The Debug Port................................221 9.2.1 JTAG-to-SWD change sequence.........................222 9.2.2 JTAG-to-cJTAG change sequence.......................222 Debug Port Pin Descriptions............................223 System TAP connection..............................223 9.4.1 IR Codes...............................223 JTAG status and control registers..........................224 9.5.1 MDM-AP Control Register..........................225...
Page 10 Section Number Title Page Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................235 10.2 Signal Multiplexing Integration............................235 10.2.1 Port control and interrupt module features....................236 10.2.2 Clock gating..............................236 10.2.3 Signal multiplexing constraints........................236 10.3 Pinout....................................237 10.3.1 K53 Signal Multiplexing and Pin Assignments...................237 10.3.2 K53 Pinouts..............................243 10.4...
Page 11 Section Number Title Page 11.4.3 Global Pin Control High Register (PORTx_GPCHR).................271 11.4.4 Interrupt Status Flag Register (PORTx_ISFR)....................271 11.4.5 Digital Filter Enable Register (PORTx_DFER)...................272 11.4.6 Digital Filter Clock Register (PORTx_DFCR)....................273 11.4.7 Digital Filter Width Register (PORTx_DFWR)..................273 11.5 Functional description..............................274 11.5.1 Pin control..............................274 11.5.2 Global pin control............................274 11.5.3...
Page 12 Section Number Title Page 12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)................300 12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)................302 12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................303 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................306 12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...................307 12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...................309 12.2.19...
Page 13 Section Number Title Page 14.3.3 Low-Voltage Warning (LVW) Interrupt Operation..................336 14.4 PMC Memory Map/Register Definition........................337 14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)............337 14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)............338 14.4.3 Regulator Status and Control Register (PMC_REGSC)................340 Chapter 15 Low-leakage wake-up unit (LLWU) 15.1...
Page 14 Section Number Title Page Chapter 16 Miscellaneous Control Module (MCM) 16.1 Introduction...................................363 16.1.1 Features................................363 16.2 Memory Map/Register Descriptions..........................363 16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..............364 16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............364 16.2.3 SRAM arbitration and protection (MCM_SRAMAP).................365 16.2.4 Interrupt status register (MCM_ISR)......................366 16.2.5 ETB counter control register (MCM_ETBCC)...................367 16.2.6...
Page 15 Section Number Title Page 18.2 Overview..................................385 18.2.1 Block Diagram.............................385 18.2.2 Features................................386 18.3 Memory Map/Register Definition..........................387 18.3.1 Control/Error Status Register (MPU_CESR)....................390 18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................392 18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)..................393 18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)................394 18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)................395 18.3.6...
Page 16 Section Number Title Page Chapter 20 Direct memory access multiplexer (DMAMUX) 20.1 Introduction...................................425 20.1.1 Overview..............................425 20.1.2 Features................................426 20.1.3 Modes of operation............................426 20.2 External signal description............................427 20.3 Memory map/register definition...........................427 20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)................428 20.4 Functional description..............................429 20.4.1 DMA channels with periodic triggering capability..................429 20.4.2 DMA channels with no triggering capability....................432 20.4.3...
Page 17 Section Number Title Page 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)..................465 21.3.7 Clear Enable Request Register (DMA_CERQ)...................466 21.3.8 Set Enable Request Register (DMA_SERQ)....................467 21.3.9 Clear DONE Status Bit Register (DMA_CDNE)..................468 21.3.10 Set START Bit Register (DMA_SSRT)......................469 21.3.11 Clear Error Register (DMA_CERR)......................470 21.3.12 Clear Interrupt Request Register (DMA_CINT)..................471 21.3.13...
Page 18 Section Number Title Page 21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)......................491 21.4 Functional description..............................492 21.4.1 eDMA basic data flow..........................492 21.4.2 Error reporting and handling........................495 21.4.3 Channel preemption.............................497 21.4.4 Performance..............................497 21.5 Initialization/application information...........................502 21.5.1 eDMA initialization.............................502 21.5.2 Programming errors.............................504 21.5.3...
Page 19 Section Number Title Page 22.4.2 The EWM_in Signal............................522 22.4.3 EWM Counter..............................522 22.4.4 EWM Compare Registers..........................522 22.4.5 EWM Refresh Mechanism...........................523 Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction...................................525 23.2 Features..................................525 23.3 Functional Overview..............................527 23.3.1 Unlocking and Updating the Watchdog.......................528 23.3.2 The Watchdog Configuration Time (WCT)....................529 23.3.3 Refreshing the Watchdog..........................530 23.3.4...
Page 20 Section Number Title Page 23.7.8 Watchdog Unlock Register (WDOG_UNLOCK)..................540 23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)..............541 23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..............541 23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................542 23.7.12 Watchdog Prescaler Register (WDOG_PRESC)..................542 23.8 Watchdog Operation with 8-bit access.........................542 23.8.1 General Guideline............................542 23.8.2...
Page 21 Section Number Title Page 24.4.3 MCG Internal Reference Clocks........................567 24.4.4 External Reference Clock..........................568 24.4.5 MCG Fixed Frequency Clock ........................568 24.4.6 MCG PLL Clock ............................569 24.4.7 MCG Auto TRIM (ATM)..........................569 24.5 Initialization / Application Information........................570 24.5.1 MCG Module Initialization Sequence......................570 24.5.2 Using a 32.768 kHz Reference........................572 24.5.3 MCG Mode Switching..........................573...
Page 22 Section Number Title Page Chapter 26 RTC Oscillator 26.1 Introduction...................................595 26.1.1 Features and Modes.............................595 26.1.2 Block Diagram.............................595 26.2 RTC Signal Descriptions..............................596 26.2.1 EXTAL32 — Oscillator Input........................596 26.2.2 XTAL32 — Oscillator Output........................596 26.3 External Crystal Connections............................597 26.4 Memory Map/Register Descriptions..........................597 26.5 Functional Description..............................597 26.6 Reset Overview................................598...
Page 23 Section Number Title Page 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)................620 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)................621 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)................622 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)................623 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)................624 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)................625 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)................626...
Page 24 Section Number Title Page 28.4.9 Flash Program and Erase..........................661 28.4.10 FTFL Command Operations........................661 28.4.11 Margin Read Commands..........................670 28.4.12 FTFL Command Description........................671 28.4.13 Security................................699 28.4.14 Reset Sequence............................701 Chapter 29 External Bus Interface (FlexBus) 29.1 Introduction...................................703 29.1.1 Overview..............................703 29.1.2 Features................................703 29.1.3 Modes of Operation.............................704 29.2 Signal Descriptions...............................704 29.2.1...
Page 25 Section Number Title Page 29.4 Functional Description..............................716 29.4.1 Chip-Select Operation..........................716 29.4.2 Data Transfer Operation..........................718 29.4.3 Data Byte Alignment and Physical Connections..................718 29.4.4 Address/Data Bus Multiplexing........................719 29.4.5 Bus Cycle Execution............................720 29.4.6 FlexBus Timing Examples...........................722 29.4.7 Burst Cycles..............................740 29.4.8 Extended Transfer Start/Address Latch Enable...................749 29.4.9 Bus Errors..............................749 29.5...
Page 26 Section Number Title Page Chapter 31 Cyclic redundancy check (CRC) 31.1 Introduction...................................763 31.1.1 Features................................763 31.1.2 Block diagram..............................763 31.1.3 Modes of operation............................764 31.2 Memory map and register descriptions.........................764 31.2.1 CRC Data Register (CRC_CRC).........................765 31.2.2 CRC Polynomial Register (CRC_GPOLY)....................766 31.2.3 CRC Control Register (CRC_CTRL)......................767 31.3 Functional description..............................768 31.3.1...
Page 27 Section Number Title Page 32.6 Functional Description..............................780 32.6.1 MMCAU Programming Model........................780 32.6.2 MMCAU Integrity Checks...........................782 32.6.3 CAU Commands............................784 32.7 Application/Initialization Information..........................791 32.7.1 Code Example..............................791 32.7.2 Assembler Equate Values..........................791 Chapter 33 Random Number Generator (RNGB) 33.1 Introduction...................................793 33.1.1 Block Diagram.............................793 33.1.2 Features................................794 33.2 Modes of Operation..............................794...
Page 28 Section Number Title Page 33.5 Initialization/Application Information..........................806 33.5.1 Manual Seeding............................806 33.5.2 Automatic Seeding............................807 Chapter 34 Analog-to-Digital Converter (ADC) 34.1 Introduction...................................809 34.1.1 Features................................809 34.1.2 Block diagram..............................810 34.2 ADC Signal Descriptions..............................811 34.2.1 Analog power (VDDA)..........................812 34.2.2 Analog ground (VSSA)..........................812 34.2.3 Voltage reference select..........................812 34.2.4 Analog channel inputs (ADx)........................813 34.2.5...
Page 29 Section Number Title Page 34.3.15 ADC plus-side general calibration value register (ADCx_CLP2)...............831 34.3.16 ADC plus-side general calibration value register (ADCx_CLP1)...............832 34.3.17 ADC plus-side general calibration value register (ADCx_CLP0)...............832 34.3.18 ADC PGA register (ADCx_PGA).......................833 34.3.19 ADC minus-side general calibration value register (ADCx_CLMD)............834 34.3.20 ADC minus-side general calibration value register (ADCx_CLMS)............835 34.3.21...
Page 30 Section Number Title Page 34.5 Initialization information..............................854 34.5.1 ADC module initialization example......................855 34.6 Application information..............................857 34.6.1 External pins and routing..........................857 34.6.2 Sources of error............................859 Chapter 35 Comparator (CMP) 35.1 Introduction...................................865 35.2 CMP Features................................865 35.3 6-bit DAC Key Features...............................866 35.4 ANMUX Key Features..............................867 35.5 CMP, DAC, and ANMUX Diagram..........................867 35.6...
Page 31 Section Number Title Page 35.12 DAC Functional Description............................892 35.12.1 Voltage Reference Source Select.........................892 35.13 DAC Resets...................................892 35.14 DAC Clocks..................................892 35.15 DAC Interrupts................................893 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.1 Introduction...................................895 36.2 Features..................................895 36.3 Block Diagram................................895 36.4 Memory Map/Register Definition..........................896 36.4.1 DAC Data Low Register (DACx_DATnL)....................900 36.4.2 DAC Data High Register (DACx_DATnH)....................901...
Page 32 Section Number Title Page 37.2 Signal Description.................................913 37.2.1 INPx+................................913 37.2.2 INPx-................................913 37.2.3 VOUTx.................................913 37.3 Memory Map and Registers............................914 37.3.1 Control Register 0 (OPAMPx_C0)......................914 37.3.2 Control Register 1 (OPAMPx_C1)......................915 37.3.3 Control Register 2 (OPAMPx_C2)......................916 37.4 Functional Description..............................917 37.4.1 Operational Amplifier Configuration......................917 37.4.2 Buffer Configuration............................917 37.4.3...
Page 33 Section Number Title Page Chapter 39 Voltage Reference (VREFV1) 39.1 Introduction...................................927 39.1.1 Overview..............................928 39.1.2 Features................................928 39.1.3 Modes of Operation.............................929 39.1.4 VREF Signal Descriptions...........................929 39.2 Memory Map and Register Definition..........................929 39.2.1 VREF Trim Register (VREF_TRM)......................930 39.2.2 VREF Status and Control Register (VREF_SC)..................931 39.3 Functional Description..............................932 39.3.1...
Page 34 Section Number Title Page 40.3.5 Channel n Control Register 1 (PDBx_CHnC1)...................945 40.3.6 Channel n Status Register (PDBx_CHnS)....................946 40.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)..................947 40.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)..................947 40.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn)..............948 40.3.10 DAC Interval n Register (PDBx_DACINTn)....................948 40.3.11 Pulse-Out n Enable Register (PDBx_POEN)....................949...
Page 35 Section Number Title Page 41.2.4 PHA — FTM Quadrature Decoder Phase A Input..................963 41.2.5 PHB — FTM Quadrature Decoder Phase B Input..................963 41.3 Memory Map and Register Definition..........................963 41.3.1 Module Memory Map..........................963 41.3.2 Register Descriptions...........................963 41.3.3 Status and Control (FTMx_SC)........................970 41.3.4 Counter (FTMx_CNT)..........................971 41.3.5...
Page 36 Section Number Title Page 41.3.27 FTM PWM Load (FTMx_PWMLOAD).....................1013 41.4 Functional Description..............................1015 41.4.1 Clock Source..............................1015 41.4.2 Prescaler...............................1016 41.4.3 Counter.................................1016 41.4.4 Input Capture Mode.............................1021 41.4.5 Output Compare Mode..........................1024 41.4.6 Edge-Aligned PWM (EPWM) Mode......................1025 41.4.7 Center-Aligned PWM (CPWM) Mode......................1027 41.4.8 Combine Mode.............................1028 41.4.9 Complementary Mode..........................1036 41.4.10...
Page 37 Section Number Title Page 41.4.28 Global Time Base (GTB)..........................1087 41.5 Reset Overview................................1088 41.6 FTM Interrupts................................1090 41.6.1 Timer Overflow Interrupt..........................1090 41.6.2 Channel (n) Interrupt............................1090 41.6.3 Fault Interrupt..............................1090 Chapter 42 Periodic Interrupt Timer (PIT) 42.1 Introduction...................................1093 42.1.1 Block Diagram.............................1093 42.1.2 Features................................1094 42.2 Signal Description.................................1094 42.3 Memory Map/Register Description..........................1095...
Page 38 Section Number Title Page 43.3 Memory map and register definition..........................1105 43.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)..............1106 43.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................1107 43.3.3 Low Power Timer Compare Register (LPTMRx_CMR)................1109 43.3.4 Low Power Timer Counter Register (LPTMRx_CNR)................1109 43.4 Functional description..............................1110 43.4.1 LPTMR power and reset..........................1110...
Page 39 Section Number Title Page 44.6.6 CMT Modulator Status and Control Register (CMT_MSC)...............1124 44.6.7 CMT Modulator Data Register Mark High (CMT_CMD1)................1125 44.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2).................1126 44.6.9 CMT Modulator Data Register Space High (CMT_CMD3)...............1126 44.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)................1127 44.6.11 CMT Primary Prescaler Register (CMT_PPS)....................1127 44.6.12...
Page 40 Section Number Title Page 45.2.10 RTC Read Access Register (RTC_RAR)....................1150 45.3 Functional description..............................1151 45.3.1 Power, clocking and reset..........................1151 45.3.2 Time counter..............................1152 45.3.3 Compensation...............................1153 45.3.4 Time alarm..............................1154 45.3.5 Update mode..............................1154 45.3.6 Register lock..............................1154 45.3.7 Access control..............................1155 45.3.8 Interrupt................................1155 Chapter 46 10/100-Mbps Ethernet MAC (ENET) 46.1 Introduction...................................1157 46.1.1...
Page 41 Section Number Title Page 46.3.12 Physical Address Upper Register (ENET_PAUR)..................1182 46.3.13 Opcode/Pause Duration Register (ENET_OPD)..................1183 46.3.14 Descriptor Individual Upper Address Register (ENET_IAUR)..............1183 46.3.15 Descriptor Individual Lower Address Register (ENET_IALR)..............1184 46.3.16 Descriptor Group Upper Address Register (ENET_GAUR)...............1184 46.3.17 Descriptor Group Lower Address Register (ENET_GALR)...............1185 46.3.18 Transmit FIFO Watermark Register (ENET_TFWR).................1185 46.3.19...
Page 42 Section Number Title Page 46.3.41 Timer Control Status Register (ENET_TCSRn)..................1200 46.3.42 Timer Compare Capture Register (ENET_TCCRn)..................1201 46.3.43 Statistic Event Counters..........................1202 46.4 Functional Description..............................1205 46.4.1 Ethernet MAC Frame Formats........................1205 46.4.2 IP and Higher Layers Frame Format......................1208 46.4.3 IEEE 1588 Message Formats........................1212 46.4.4 MAC Receive...............................1216 46.4.5...
Page 43 Section Number Title Page 47.2 Functional Description..............................1265 47.2.1 Data Structures.............................1265 47.3 Programmers Interface..............................1266 47.3.1 Buffer Descriptor Table..........................1266 47.3.2 Rx vs. Tx as a USB Target Device or USB Host..................1267 47.3.3 Addressing Buffer Descriptor Table Entries....................1268 47.3.4 Buffer Descriptor Formats...........................1268 47.3.5 USB Transaction............................1271 47.4 Memory Map/Register Definitions..........................1273...
Page 44 Section Number Title Page 47.4.21 BDT Page Register 2 (USBx_BDTPAGE2)....................1292 47.4.22 BDT Page Register 3 (USBx_BDTPAGE3)....................1292 47.4.23 Endpoint Control Register (USBx_ENDPTn).....................1292 47.4.24 USB Control Register (USBx_USBCTRL)....................1294 47.4.25 USB OTG Observe Register (USBx_OBSERVE)..................1294 47.4.26 USB OTG Control Register (USBx_CONTROL)..................1295 47.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0)................1296 47.5 OTG and Host Mode Operation............................1297 47.6...
Page 45 Section Number Title Page 48.4.5 USBDCD_TIMER1.............................1315 48.4.6 USBDCD_TIMER2.............................1315 48.5 Functional Description..............................1316 48.5.1 The Charger Detection Sequence.........................1317 48.5.2 Interrupts and Events...........................1327 48.5.3 Resets................................1328 48.6 Initialization Information..............................1329 48.7 Application Information..............................1329 48.7.1 External Pullups............................1329 48.7.2 Dead or Weak Battery..........................1329 48.7.3 Handling Unplug Events..........................1330 Chapter 49 USB Voltage Regulator 49.1...
Page 46 Section Number Title Page 50.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe.............1341 50.2.5 SIN — Serial Input............................1341 50.2.6 SOUT — Serial Output..........................1341 50.2.7 SCK — Serial Clock............................1341 50.3 Memory Map/Register Definition..........................1342 50.3.1 DSPI Module Configuration Register (SPIx_MCR)..................1345 50.3.2 DSPI Transfer Count Register (SPIx_TCR)....................1348 50.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)........1348...
Page 47 Section Number Title Page 50.5.4 Delay Settings..............................1384 50.5.5 Calculation of FIFO Pointer Addresses.......................1385 Chapter 51 Inter-Integrated Circuit (I2C) 51.1 Introduction...................................1389 51.1.1 Features................................1389 51.1.2 Modes of Operation.............................1390 51.1.3 Block Diagram.............................1390 51.2 I2C Signal Descriptions..............................1391 51.3 Memory Map and Register Descriptions........................1391 51.3.1 I2C Address Register 1 (I2Cx_A1)......................1393 51.3.2 I2C Frequency Divider register (I2Cx_F)....................1393...
Page 48 Section Number Title Page 51.4.6 Interrupts..............................1414 51.4.7 Programmable Input Glitch Filter........................1416 51.4.8 Address Matching Wakeup..........................1416 51.4.9 DMA Support...............................1417 51.5 Initialization/Application Information..........................1417 Chapter 52 Universal Asynchronous Receiver/Transmitter (UART) 52.1 Introduction...................................1421 52.1.1 Features................................1421 52.1.2 Modes of operation............................1423 52.2 UART signal descriptions.............................1424 52.2.1 Detailed signal descriptions.........................1424 52.3 Memory map and registers............................1425...
Page 49 Section Number Title Page 52.3.17 UART FIFO Control Register (UARTx_CFIFO)..................1457 52.3.18 UART FIFO Status Register (UARTx_SFIFO)...................1458 52.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)................1459 52.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)..................1460 52.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)................1460 52.3.22 UART FIFO Receive Count (UARTx_RCFIFO)..................1461 52.3.23 UART 7816 Control Register (UARTx_C7816)..................1462 52.3.24...
Page 50 Section Number Title Page 52.8 Application information..............................1505 52.8.1 Transmit/receive data buffer operation......................1505 52.8.2 ISO-7816 initialization sequence.........................1506 52.8.3 Initialization sequence (non ISO-7816).......................1508 52.8.4 Overrun (OR) flag implications........................1509 52.8.5 Overrun NACK considerations........................1510 52.8.6 Match address registers..........................1511 52.8.7 Modem feature.............................1511 52.8.8 IrDA minimum pulse width.........................1512 52.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts................1512 52.8.10...
Page 51 Section Number Title Page 53.4.9 Buffer Data Port Register (SDHC_DATPORT)..................1531 53.4.10 Present State Register (SDHC_PRSSTAT)....................1531 53.4.11 Protocol Control Register (SDHC_PROCTL).....................1536 53.4.12 System Control Register (SDHC_SYSCTL)....................1540 53.4.13 Interrupt Status Register (SDHC_IRQSTAT).....................1543 53.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)................1549 53.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)................1552 53.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)................1554 53.4.17...
Page 52 Section Number Title Page 53.6.2 Card identification mode..........................1590 53.6.3 Card access..............................1595 53.6.4 Switch function............................1606 53.6.5 ADMA operation............................1608 53.6.6 Fast boot operation............................1609 53.6.7 Commands for MMC/SD/SDIO/CE-ATA....................1613 53.7 Software restrictions..............................1619 53.7.1 Initialization active............................1619 53.7.2 Software polling procedure..........................1620 53.7.3 Suspend operation............................1620 53.7.4 Data length setting............................1620 53.7.5 (A)DMA address setting..........................1620 53.7.6...
Page 53 Section Number Title Page 54.3.7 S Interrupt Enable Register (I2Sx_IER)....................1643 54.3.8 S Transmit Configuration Register (I2Sx_TCR)..................1647 54.3.9 S Receive Configuration Register (I2Sx_RCR)..................1649 54.3.10 S Transmit Clock Control Registers (I2Sx_TCCR)..................1651 54.3.11 S Receive Clock Control Registers (I2Sx_RCCR)...................1653 54.3.12 S FIFO Control/Status Register (I2Sx_FCSR)..................1654 54.3.13 S AC97 Control Register (I2Sx_ACNT)....................1660 54.3.14...
Page 54 Section Number Title Page 55.1.2 Modes of operation............................1695 55.1.3 GPIO signal descriptions..........................1696 55.2 Memory map and register definition..........................1697 55.2.1 Port Data Output Register (GPIOx_PDOR)....................1700 55.2.2 Port Set Output Register (GPIOx_PSOR)....................1700 55.2.3 Port Clear Output Register (GPIOx_PCOR)....................1701 55.2.4 Port Toggle Output Register (GPIOx_PTOR).....................1701 55.2.5 Port Data Input Register (GPIOx_PDIR).....................1702 55.2.6...
Page 55 Section Number Title Page 56.6.2 SCAN control register (TSIx_SCANC).......................1715 56.6.3 Pin enable register (TSIx_PEN)........................1718 56.6.4 Status Register (TSIx_STATUS).........................1721 56.6.5 Counter Register (TSIx_CNTRn)........................1724 56.6.6 Channel n threshold register (TSIx_THRESHLDn)..................1725 56.7 Functional descriptions..............................1725 56.7.1 Capacitance measurement..........................1725 56.7.2 TSI measurement result..........................1728 56.7.3 Electrode scan unit............................1729 56.7.4 Touch detection unit.............................1732 56.8...
Page 56 Section Number Title Page 57.3.7 LCD waveform register (LCD_WF3TO0)....................1751 57.3.8 LCD waveform register (LCD_WF7TO4)....................1752 57.3.9 LCD waveform register (LCD_WF11TO8)....................1752 57.3.10 LCD waveform register (LCD_WF15TO12)....................1753 57.3.11 LCD waveform register (LCD_WF19TO16)....................1754 57.3.12 LCD waveform register (LCD_WF23TO20)....................1754 57.3.13 LCD waveform register (LCD_WF27TO24)....................1755 57.3.14 LCD waveform register (LCD_WF31TO28)....................1756 57.3.15 LCD waveform register (LCD_WF35TO32)....................1756...
Page 57 Section Number Title Page 57.5.2 Initialization Examples..........................1788 57.6 Application information..............................1794 57.6.1 LCD seven segment example description....................1795 57.6.2 LCD contrast control............................1798 Chapter 58 JTAG Controller (JTAGC) 58.1 Introduction...................................1801 58.1.1 Block diagram..............................1801 58.1.2 Features................................1802 58.1.3 Modes of operation............................1802 58.2 External signal description............................1804 58.2.1 TCK—Test clock input..........................1804 58.2.2...
Page 58 K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 59: About This Document
Chapter 1 About This Document Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K53 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K53 microcontroller in a system. Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:...
Page 60: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 61: Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis portfolio and K50 family of products. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 K50 Family Introduction The K50 MCU family includes a flexible, low-power segment LCD controller with support for up to 320 segments, analog front end capability, and full-speed USB 2.0 On- The-Go with device charger detect capability.
Page 62 Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description System • System integration module • Power management and mode controllers • Multiple power modes available based on run, wait, stop, and power- down modes • Low-leakage wakeup unit •...
Page 63: Arm Cortex-M4 Core Modules
Chapter 2 Introduction Table 2-1. Module functional categories (continued) Module category Description Human-Machine Interfaces (HMI) • General purpose input/output controller • Capacitive touch sense input interface enabled in hardware • Segment LCD controller 2.3.1 ARM Cortex-M4 Core Modules The following core modules are available on this device. Table 2-2.
Page 64: Memories And Memory Interfaces
Module Functional Categories Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. Mode controller The MC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU.
Page 65: Clocks
Chapter 2 Introduction Table 2-4. Memories and memory interfaces Module Description Flash memory • Program flash memory — non-volatile flash memory that can execute program code • FlexMemory — encompasses the following memory types: • For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can execute program code, store data, or backup EEPROM data •...
Page 66: Security And Integrity Modules
Module Functional Categories 2.3.5 Security and Integrity modules The following security and integrity modules are available on this device: Table 2-6. Security and integrity modules Module Description Cryptographic acceleration unit (CAU) Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms via simple C calls to optimized security functions provided by Freescale.
Page 67 Chapter 2 Introduction Table 2-8. Timer modules Module Description Programmable delay block (PDB) • 16-bit resolution • 3-bit prescaler • Positive transition of trigger event signal initiates the counter • Supports two triggered delay output signals, each with an independently- controlled delay from the trigger event •...
Page 68: Communication Interfaces
Module Functional Categories Table 2-8. Timer modules (continued) Module Description Real-time clock (RTC) • Independent power supply, POR, and 32 kHz Crystal Oscillator • 32-bit seconds counter with 32-bit Alarm • 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm IEEE 1588 timers •...
Page 69: Orderable Part Numbers
Chapter 2 Introduction Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 5 V tolerance. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications.
Page 70 Orderable part numbers K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 71: Chip Configuration
Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and •...
Page 72 Core modules Debug Interrupts SRAM Upper ARM Cortex-M4 Crossbar switch Core SRAM Lower Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, http://www.arm.com r0p0 System memory map System memory map Clocking Clock distribution Power management...
Page 73 Chapter 3 Chip Configuration Bus name Description Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. In addition, the CODE bus is also Data code (DCODE) bus tightly coupled to the lower half of the system RAM (SRAM_L).
Page 74: Nested Vectored Interrupt Controller (Nvic) Configuration
Core modules 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. Interrupts Module Nested Vectored Module Interrupt Controller (NVIC)
Page 75 Chapter 3 Chip Configuration 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus The IRQ number is used within ARM's NVIC documentation.
Page 76 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0054 DMA channel 5 transfer complete 0x0000_0058 DMA channel 6 transfer complete 0x0000_005C DMA channel 7 transfer complete 0x0000_0060 DMA channel 8 transfer complete 0x0000_0064 DMA channel 9 transfer complete...
Page 77 Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_00C4 — — 0x0000_00C8 — — 0x0000_00CC — — 0x0000_00D0 — — 0x0000_00D4 — — 0x0000_00D8 — —...
Page 78 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_0128 ADC1 — 0x0000_012C CMP0 — 0x0000_0130 CMP1 — 0x0000_0134 CMP2 — 0x0000_0138 FTM0 Single interrupt vector for all sources 0x0000_013C FTM1 Single interrupt vector for all sources...
Page 79 Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector NVIC NVIC Source module Source description non-IPR register register number number 0x0000_01A0 Port control Pin detect (Port B) module 0x0000_01A4 Port control Pin detect (Port C) module 0x0000_01A8 Port control Pin detect (Port D) module...
Page 80: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Core modules • NVICIABR2 • NVICIPR21 • To determine the particular IRQ's bitfield location within these particular registers: • NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit location = IRQ mod 32 = 21 • NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21...
Page 81: Jtag Controller Configuration
Chapter 3 Chip Configuration Table 3-6. Reference links to related information (continued) Topic Related module Reference Power management Power management Nested Vectored NVIC Interrupt Controller (NVIC) Wake-up requests AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7.
Page 82: System Modules
System modules JTAG controller Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing System modules 3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 83: Mode Controller Configuration
Chapter 3 Chip Configuration 3.3.2 Mode Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Resets Mode controller Figure 3-6.
Page 84: Low-Leakage Wake-Up Unit (Llwu) Configuration
System modules Peripheral bridge Register access Power management controller (PMC) Figure 3-7. PMC configuration Table 3-11. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Full description Mode Controller Mode Controller Low-Leakage Wakeup LLWU...
Page 85 Chapter 3 Chip Configuration Table 3-12. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management chapter Power Management Power Management Controller (PMC) Controller (PMC) Mode Controller Mode Controller Wake-up requests LLWU wake-up sources 3.3.4.1 Wake-up Sources This chip uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module:...
Page 86: Mcm Configuration
System modules up the MCU from any non-VLLSx mode with the NMI function selected in its port control register asserts an NMI exception on low power mode recovery. The same occurs when recovering from VLLSx modes if EzPort is disabled; otherwise, EzPort mode is entered.
Page 87 Chapter 3 Chip Configuration Master Modules Slave Modules Crossbar Switch ARM core code bus Flash controller ARM core system bus SRAM backdoor EzPort Peripheral bridge 0 Peripheral Ethernet bridge 1 GPIO controller FlexBus SDHC Figure 3-10. Crossbar switch integration Table 3-15. Reference links to related information Topic Related module Reference...
Page 88 System modules Table 3-15. Reference links to related information (continued) Topic Related module Reference Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus FlexBus 3.3.6.1 Crossbar Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus...
Page 89: Memory Protection Unit (Mpu) Configuration
Chapter 3 Chip Configuration 3.3.7 Memory Protection Unit (MPU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Transfers Transfers Logical...
Page 90 System modules 3.3.7.2 MPU Logical Bus Master Assignments The logical bus master assignments for the MPU are: Table 3-18. MPU Logical Bus Master Assignments MPU Logical Bus Master Number Bus Master Core Debugger ENET SDHC none none 3.3.7.3 MPU Access Violation Indications Access violations detected by the MPU are signaled to the appropriate bus master as shown below: Table 3-19.
Page 91: Peripheral Bridge Configuration
Chapter 3 Chip Configuration Table 3-20. Reset Values for RGD0 Registers Register Reset value RGD0_WORD0 0000_0000h RGD0_WORD1 FFFF_FFFFh RGD0_WORD2 0061_F7DFh RGD0_WORD3 0000_0001h RGDAAC0 0061_F7DFh 3.3.7.5 Write Access Restrictions for RGD0 Registers In addition to configuring the initial state of RGD0, the MPU implements further access control on writes to the RGD0 registers.
Page 92 System modules Transfers Transfers AIPS-Lite peripheral bridge Figure 3-12. Peripheral bridge configuration Table 3-22. Reference links to related information Topic Related module Reference Full description Peripheral bridge Peripheral bridge (AIPS-Lite) (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch...
Page 93: Dma Request Multiplexer Configuration
Chapter 3 Chip Configuration 3.3.8.5 PACR registers Each of the two peripheral bridges support up to 128 peripherals each assigned to an PACRx field within the PACRA-PACRP registers. However, fewer peripherals are supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of the peripheral slot assignments for this device.
Page 94 System modules 3.3.9.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel.
Page 95 Chapter 3 Chip Configuration Table 3-24. DMA request sources - MUX 0 (continued) Source Source module Source description number FTM0 Channel 3 FTM0 Channel 4 FTM0 Channel 5 FTM0 Channel 6 FTM0 Channel 7 FTM1 Channel 0 FTM1 Channel 1 FTM2 Channel 0 FTM2...
Page 96: Dma Controller Configuration
System modules Table 3-24. DMA request sources - MUX 0 (continued) Source Source module Source description number DMA MUX Always enabled DMA MUX Always enabled DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. 3.3.9.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels.
Page 97: External Watchdog Monitor (Ewm) Configuration
Chapter 3 Chip Configuration 3.3.11 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals External Watchdog Monitor (EWM)
Page 98: Watchdog Configuration
System modules Table 3-28. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS Power Down VLLS3, VLLS2, VLLS1 3.3.11.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state.
Page 99: Clock Modules
Chapter 3 Chip Configuration 3.3.12.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-30. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock...
Page 100: Osc Configuration
Clock Modules Peripheral bridge Register access Multipurpose Clock Generator (MCG) Figure 3-17. MCG configuration Table 3-32. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing...
Page 101: Rtc Osc Configuration
Chapter 3 Chip Configuration Table 3-33. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details.
Page 102 Memories and Memory Interfaces Peripheral bus controller 0 Register access Transfers Flash memory Figure 3-20. Flash memory configuration Table 3-35. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers...
Page 103 Chapter 3 Chip Configuration • For devices that contain FlexNVM: 1 block of program flash consisting of 2 KB sectors • For devices that contain FlexNVM: 1 block of FlexNVM consisting of 2 KB sectors • For devices that contain FlexNVM: 1 block of FlexRAM The amounts of flash memory for the devices covered in this document are: Device Program...
Page 104 Memories and Memory Interfaces 3.5.1.4 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field...
Page 105: Flash Memory Controller Configuration
Chapter 3 Chip Configuration 3.5.1.7 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory in two ways: 1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for more details.
Page 106: Sram Configuration
Memories and Memory Interfaces Table 3-36. Reference links to related information (continued) Topic Related module Reference Transfers Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters.
Page 107 Chapter 3 Chip Configuration Cortex-M4 SRAM upper core Transfers Crossbar SRAM lower switch Figure 3-24. SRAM configuration Table 3-37. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller...
Page 108 Memories and Memory Interfaces Valid address ranges for SRAM_L and SRAM_U are then defined as: • SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF • SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1] This is illustrated in the following figure. 0x2000_0000 – SRAM_size/2 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size/2 - 1 Figure 3-25.
Page 109 Chapter 3 Chip Configuration The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). The following figure illustrates the SRAM accesses within the device. SRAM_L Cortex-M4 core Crossbar switch non-core master Frontdoor Backdoor Code bus non-core master SRAM controller System bus...
Page 110: Sram Controller Configuration
Memories and Memory Interfaces 3.5.4 SRAM Controller Configuration This section summarizes how the module has been configured in the chip. Cortex-M4 core SRAM controller Transfers Crossbar switch Figure 3-27. SRAM controller configuration Table 3-38. Reference links to related information Topic Related module Reference System memory map...
Page 111 Chapter 3 Chip Configuration Peripheral bridge 0 Register access Register file Figure 3-28. System Register file configuration Table 3-39. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management...
Page 112 Memories and Memory Interfaces Peripheral bridge Register access VBAT register file Figure 3-29. VBAT Register file configuration Table 3-40. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management...
Page 113 Chapter 3 Chip Configuration Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.7.1 JTAG instruction The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode.
Page 114 Memories and Memory Interfaces Peripheral bridge 0 Register access Module signals Transfers FlexBus Figure 3-31. FlexBus configuration Table 3-42. Reference links to related information Topic Related module Reference Full description FlexBus FlexBus System memory map System memory map Clocking Clock distribution Power management Power management Transfers...
Page 115 Chapter 3 Chip Configuration FlexBus Port Control Module CSPMCR FB_ALE FB_CS1 Group1 FB_TS Reserved FB_CS4 FB_TSIZ0 Group2 FB_BE_31_24 Reserved FB_CS5 FB_TSIZ1 Group3 FB_BE_23_16 Reserved FB_TBST FB_CS2 Group4 FB_BE_15_8 Reserved FB_TA FB_CS3 Group5 FB_BE_7_0 Reserved Figure 3-32. FlexBus control signal multiplexing K53 Sub-Family Reference Manual, Rev.
Page 116 Security Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function.
Page 117 Chapter 3 Chip Configuration Peripheral bridge Register access Figure 3-33. CRC configuration Table 3-43. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management 3.6.2 MMCAU Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 118: Analog
Analog 3.6.3 RNG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Random number generator Figure 3-35. RNG configuration Table 3-45.
Page 119 Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Module signals Transfers 16-bit SAR ADC Other peripherals Figure 3-36. 16-bit SAR ADC with PGA configuration Table 3-46. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC with 16-bit SAR ADC with PGA System memory map System memory map...
Page 120 Analog 3.7.1.3 ADC0 Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1 ADC0 Channel Assignment for 144-Pin Package ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1)
Page 121 Chapter 3 Chip Configuration ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E) 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110...
Page 122 Analog ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 00111 AD7b Reserved ADC1_SE7b 01000 Reserved ADC1_SE8 01001 Reserved ADC1_SE9 01010 AD10 Reserved ADC1_SE10 01011 AD11 Reserved ADC1_SE11 01100 AD12 Reserved ADC1_SE12 01101 AD13 Reserved ADC1_SE13 01110 AD14 Reserved ADC1_SE14...
Page 123 Chapter 3 Chip Configuration AD4 [00100] ADCx_SE4a ADCx_SE5a AD5 [00101] ADCx_SE6a ADCx_SE7a AD6 [00110] ADCx_SE4b ADCx_SE5b AD7 [00111] ADCx_SE6b ADCx_SE7b Figure 3-37. ADCx_SEn channels a and b selection 3.7.1.6 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration.
Page 124 Analog • VREFH/VREFL - connected as the primary reference option • 1.2 V VREF_OUT - connected as the V reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. The only reference option for the PGA is the 1.2 V VREF_OUT source.
Page 125 Chapter 3 Chip Configuration Table 3-47. ADC low-power modes Module mode Chip mode Wait Wait, VLPW Normal Stop Stop, VLPS Low Power Stop LLS, VLLS3, VLLS2, VLLS1 3.7.1.11 PGA Integration • No additional external pins are required for the PGA as it is part of the ADC and is selected as a separate channel •...
Page 126: Cmp Configuration
Analog ADC0 ADC0_DP1 DAD1 ADC0_DM1 DAD0 PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0 DAD2 PGA0_DM/ADC0_DM0/ADC1_DM3 DAD3 ADC1 DAD3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1 DAD2 PGA1_DM/ADC1_DM0/ADC0_DM3 DAD0 ADC1_DP1 DAD1 ADC1_DM1 Figure 3-39. PGA Integration 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 127 Chapter 3 Chip Configuration Peripheral bridge 0 Register access Module signals Other peripherals Figure 3-40. CMP configuration Table 3-48. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management...
Page 128: 12-Bit Dac Configuration
Analog 3.7.2.3 External window/sample input PDB pulse-out controls the CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Register...
Page 129: Op-Amp Configuration
Chapter 3 Chip Configuration 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options.
Page 130 Analog 3.7.4.2 Op-amp 0 input mux connections The op-amp 0 module contains multiplexers for selecting the positive and negative inputs. The inputs to these muxes are defined as follows: Op-amp 0 minus input number Signal connection OP0_DM0 input signal (default) Reserved Op-amp 1 output CMP0 6-bit DAC output...
Page 131: Triamp Configuration
Chapter 3 Chip Configuration Op-amp 1 positive input number Signal connection OP1_DP0 input signal Op-amp 0 output Op-amp 1 output CMP0 6-bit DAC output 12-bit DAC0 output 12-bit DAC1 Output Ground 3.7.4.4 Op-amp output connections The op-amp module output is optionally available as follows: Op-amp number Op-amp output signal connection CMP1 input...
Page 132: Vref Configuration
Analog Peripheral bridge Register access Module signals TRIAMP Figure 3-43. TRIAMP configuration Table 3-51. Reference links to related information Topic Related module Reference Full description TRIAMP TRIAMP System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing...
Page 133: Timers
Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Module signals Transfers VREF Other peripherals Figure 3-44. VREF configuration Table 3-52. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management...
Page 134 Timers Peripheral bus controller 0 Register access Module signals Transfers Other peripherals Figure 3-45. PDB configuration Table 3-53. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control...
Page 135 Chapter 3 Chip Configuration Table 3-55. PDB Input Trigger Options (continued) PDB Trigger PDB Input 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 Init and Ext Trigger Outputs 1001 FTM1 Init and Ext Trigger Outputs 1010 FTM2 Init and Ext Trigger Outputs 1011...
Page 136 Timers Channel 0 pre-trigger 0 Channel 1 Channel 0 pre-trigger 1 pre-trigger 1 Channel 1 pre-trigger 0 Figure 3-46. PDB back-to-back chain The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pre- triggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows.
Page 137: Flextimer Configuration
Chapter 3 Chip Configuration 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-56. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 0 - POEN 31:8 - Reserved 31:1 - Reserved...
Page 138 Timers Table 3-58. FTM Instantiations FTM instance Number of channels Features/usage FTM0 3-phase motor + 2 general purpose or stepper motor FTM1 Quadrature decoder or general purpose FTM2 Quadrature decoder or general purpose Compared with the FTM0 configuration, the FTM1 and FTM2 configuration adds the Quadrature decoder feature and reduces the number of channels.
Page 139 Chapter 3 Chip Configuration • FTM1 FAULT1 = CMP1 output • FTM1 FAULT2 = CMP2 output • FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output • FTM2 FAULT1 = CMP1 output • FTM2 FAULT2 = CMP2 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: •...
Page 140: Pit Configuration
Timers FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: FTM1 CONF Register GTBEOUT = 0 FTM0 FTM Counter GTBEEN = 1 CONF Register gtb_in gtb_in GTBEOUT = 1...
Page 141: Low-Power Timer Configuration
Chapter 3 Chip Configuration Table 3-59. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-60.
Page 142 Timers Peripheral bridge Register access Module signals Low-power timer Figure 3-50. LPT configuration Table 3-61. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control...
Page 143: Cmt Configuration
Chapter 3 Chip Configuration 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin...
Page 144: Rtc Configuration
Timers 3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[CMTUARTPAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin.
Page 145: Communication Interfaces
Chapter 3 Chip Configuration 3.8.6.3 RTC seconds interrupt The RTC seconds interrupt is not supported on this device. Communication interfaces 3.9.1 Ethernet Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 1 Register...
Page 146 Communication interfaces • An externally-supplied 25 MHz MII clock or 50 MHz RMII clock. This clock is used as the timing reference for the external MII or RMII interface. • A time-stamping clock for the IEEE 1588 timers. For more details on the Ethernet module clocking options, see Ethernet Clocking.
Page 147: Universal Serial Bus (Usb) Subsystem
Chapter 3 Chip Configuration 3.9.1.4.1 IEEE 1588 Timer Operation in Low Power Modes The 1588 counter and 1588 timer channels can continue operating in low power modes provided their clock is enabled in that mode. The 1588 timer channels can also generate an interrupt to exit the low power mode if the clock is enabled in that mode.
Page 148 Communication interfaces • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification. • USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for host mode functionality.
Page 149 Chapter 3 Chip Configuration 2 AA Cells To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP USB0_DM Controller XCVR Figure 3-55. USB regulator AA cell usecase 3.9.2.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD.
Page 150 Communication interfaces To PMC and Pads VOUT33 stab Chip TYPE A VREGIN VBUS Si2301 Charger Regulator USB0_DP Controller XCVR USB0_DM Li-Ion VBUS Sense Charger Detect Figure 3-56. USB regulator Li-ion usecase 3.9.2.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD.
Page 151 Chapter 3 Chip Configuration 3.9.2.3 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. This can be done by setting the SIM_SOPT1[USBSTBY] bit. 3.9.2.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 152 Communication interfaces Peripheral bridge 0 Register access USB Device Charger Detect Figure 3-59. USB DCD configuration Table 3-66. Reference links to related information Topic Related module Reference Full description USB DCD USB DCD System memory map System memory map Clocking Clock Distribution USB controller USB controller...
Page 153: Spi Configuration
Chapter 3 Chip Configuration NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.3 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 154 Communication interfaces 3.9.3.3 Number of CTARs SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers. This device supports two CTARs on all instances of the SPI. In master mode, the CTAR registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays.
Page 155 Chapter 3 Chip Configuration Table 3-71. SPI PCS signals (continued) SPI Module PCS Signals SPI2 SPI_PCS[1:0] 3.9.3.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 1MHz.
Page 156: I2C Configuration
Communication interfaces 3.9.3.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.3.10 SPI clocks This table shows the SPI module clocks and the corresponding chip clocks.
Page 157: Uart Configuration
Chapter 3 Chip Configuration 3.9.4.1 Number of I2C modules This device has two I C modules. 3.9.5 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register...
Page 158 Communication interfaces 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports open-drain for all I/O. 6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs 7.
Page 159: Sdhc Configuration
Chapter 3 Chip Configuration Source UART 0 UART 1 UART 2 UART 3 UART 4 UART 5 Parity error Transmitter buffer overflow Receiver buffer underflow Transmit — — — — — threshold (ISO7816) Receiver — — — — — threshold (ISO7816) Wait timer —...
Page 160: I2S Configuration
Communication interfaces Table 3-75. Reference links to related information (continued) Topic Related module Reference Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.9.6.1 SDHC clocking In addition to the system clock, the SDHC needs a clock for the base for the external card clock.
Page 161 Chapter 3 Chip Configuration Peripheral bridge Register access Module signals Figure 3-65. I S configuration Table 3-76. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing...
Page 162: Human-Machine Interfaces (Hmi)
Human-machine interfaces (HMI) 3.9.7.3 I S clock generation To generate the desired frequencies for the I S module there are multiple clocking options as shown below: • The core/system clock is routed to an 8-bit fractional divider to generate the I clock.
Page 163: Tsi Configuration
Chapter 3 Chip Configuration Peripheral bridge Register access Transfers Module signals GPIO controller Figure 3-66. GPIO configuration Table 3-77. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers...
Page 164 Human-machine interfaces (HMI) Peripheral bridge Register access Module signals Touch sense input module Figure 3-67. TSI configuration Table 3-78. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control...
Page 165 Chapter 3 Chip Configuration Table 3-79. TSI module functionality in MCU operation modes (continued) MCU operation mode TSI clock sources TSI operation mode Functional electrode Required when GENCS[TSIEN] pins GENCS[STPE] state is 1 VLPS OSCERCLK Active mode LPOCLK, Low power mode Determined by VLPOSCCLK PEN[LPSP]...
Page 166: Segment Lcd Configuration
Human-machine interfaces (HMI) 3.10.3 Segment LCD Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Register access Module signals Segment LCD Figure 3-68.
Page 167 Chapter 3 Chip Configuration See the Signal Multiplexing and Signal Descriptions chapter for the number of LCD pins used in this MCU. 3.10.3.3 LCD pin enable, backplane enable, and waveform registers The following table shows the comparison of LCD pin enable, backplane enable, and waveform registers at the module and chip level.
Page 168 Human-machine interfaces (HMI) K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 169: Memory Map
Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
Page 170: Aliased Bit-Band Regions
System memory map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0x4008_0000–0x400F_EFFF Bitband region for peripheral bridge 1 (AIPS-Lite1) Cortex-M4 core & DMA/EzPort 0x400F_F000–0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core & DMA/EzPort 0x4010_0000–0x41FF_FFFF Reserved –...
Page 171: Flash Memory Map
Chapter 4 Memory Map • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Bit-band region Alias bit-band region Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region.
Page 172: Alternate Non-Volatile Irc User Trim Description
Flash Memory Map Flash memory base address Registers Program flash base address Flash configuration field Program flash Programming acceleration RAM base address Figure 4-2. Flash memory map for devices containing only program flash Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address...
Page 173: Sram Memory Map
Chapter 4 Memory Map 4.4 SRAM memory map The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Arrays for details.
Page 174 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps 4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 Peripheral bridge 0 (AIPS-Lite 0) 0x4000_1000 — 0x4000_2000 — 0x4000_3000 —...
Page 175 Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4002_1000 DMA channel mutiplexer 0 0x4002_2000 — 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 — 0x4002_A000 —...
Page 176 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4004_3000 — 0x4004_4000 — 0x4004_5000 Touch sense interface (TSI) 0x4004_6000 — 0x4004_7000 SIM low-power logic 0x4004_8000 System integration module (SIM) 0x4004_9000 Port A multiplexing control 0x4004_A000...
Page 177: Peripheral Bridge 1 (Aips-Lite 1) Memory Map
Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4006_5000 System oscillator (OSC) 0x4006_6000 0x4006_7000 0x4006_8000 0x4006_9000 — 0x4006_A000 UART 0 0x4006_B000 UART 1 0x4006_C000 UART 2 0x4006_D000 UART 3 0x4006_E000 —...
Page 178 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x4008_1000 — 0x4008_2000 — 0x4008_3000 — 0x4008_4000 — 0x4008_5000 — 0x4008_6000 — 0x4008_7000 — 0x4008_8000 — 0x4008_9000 — 0x4008_A000 —...
Page 179 Chapter 4 Memory Map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400A_3000 — 0x400A_4000 — 0x400A_5000 — 0x400A_6000 — 0x400A_7000 — 0x400A_8000 — 0x400A_9000 — 0x400A_A000 — 0x400A_B000 — 0x400A_C000 SPI 2 0x400A_D000 —...
Page 180 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400C_5000 — 0x400C_6000 — 0x400C_7000 — 0x400C_8000 — 0x400C_9000 — 0x400C_A000 — 0x400C_B000 — 0x400C_C000 12-bit digital-to-analog converter (DAC) 0 0x400C_D000 12-bit digital-to-analog converter (DAC) 1 0x400C_E000...
Page 181 Chapter 4 Memory Map Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot Module number 0x400E_7000 — 0x400E_8000 — 0x400E_9000 — 0x400E_A000 UART 4 0x400E_B000 UART 5 0x400E_C000 — 0x400E_D000 — 0x400E_E000 — 0x400E_F000 — 0x400F_0000 —...
Page 182: Private Peripheral Bus (Ppb) Memory Map
Private Peripheral Bus (PPB) memory map 4.6 Private Peripheral Bus (PPB) memory map The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them.
Page 183: Clock Distribution
Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules.
Page 184: Clock Definitions
Clock definitions Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 4 MHz IRC ÷2 Clock options for MCGIRCLK some peripherals MCGFFCLK 32 kHz IRC ÷2 (see note) Core / system clocks OUTDIV1 Bus clock OUTDIV2 MCGOUTCLK FlexBus clock...
Page 185: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK...
Page 186 Clock definitions Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency FlexBus clock Up to 50 MHz Up to 2 MHz MCGOUTCLK clock In all stop modes or divider (FB_CLK) FlexBus disabled...
Page 187: Internal Clocking Requirements
Chapter 5 Clock Distribution Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency Ethernet IEEE 1588 Up to 100 MHz System clock, Ethernet is disabled clock OSCERCLK, MCGPLLCLK/ MCGFLLCLK, or ENET_1588_CLKIN TRACE clock...
Page 188: Clock Divider Values After Reset
Internal clocking requirements Clock Frequency System clock 100 MHz Bus clock 50 MHz FlexBus clock 25 MHz Flash clock 25 MHz Option 3: Clock Frequency Core clock 96 MHz System clock 96 MHz Bus clock 48 MHz FlexBus clock 48 MHz Flash clock 24 MHz 5.5.1 Clock divider values after reset...
Page 189: Clock Gating
Chapter 5 Clock Distribution 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock.
Page 190 Module clocks Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Clocks Bus clock MCGOUTCLK, — MCGPLLCLK, MCGFLLCLK, MCGIRCLK, OSCERCLK Bus clock OSCERCLK — Memory and memory interfaces Flash Controller System clock Flash clock — Flash memory Flash clock —...
Page 191: Pmc 1-Khz Lpo Clock
Chapter 5 Clock Distribution Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks UART2-5 Bus clock — — SDHC System clock SDHC clock SDHC_DCLK Bus clock S master clock I2S_TX_BCLK, I2S_RX_BCLK Human-machine interfaces GPIO System clock —...
Page 192: Port Digital Filter Clocking
Module clocks MCGOUTCLK TPIU TRACECLKIN TRACE_CLKOUT ÷2 Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3. Trace clock generation NOTE The trace clock frequency observed at the TRACE_CLKOUT pin will be half that of the selected clock source. 5.7.4 PORT digital filter clocking The digital filters in each of the PORTx modules can be clocked as shown in the following figure.
Page 193: Ethernet Clocking
Chapter 5 Clock Distribution NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MCGIRCLK LPTMRx prescaler/glitch filter clock ERCLK32K OSCERCLK LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.6 Ethernet Clocking •...
Page 194: Usb Fs Otg Controller Clocking
Module clocks 5.7.7 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its clock is connected to the system clock. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz.
Page 195: I2S Clocking
Chapter 5 Clock Distribution Core / system clock MCGPLLCLK or MCGFLLCLK SDHC clock OSCERCLK SDHC0_CLKIN SIM_SOPT2[SDHCSRC] Figure 5-8. SDHC clock generation 5.7.10 I S clocking In addition to the bus clock, the I S has a clock source for master clock generation. The maximum frequency of this clock is 50 MHz.
Page 196 Module clocks Bus clock TSI clock MCGIRCLK in active mode OSCERCLK TSI_SCANC[AMCLKS] Figure 5-10. TSI clock generation In low-power mode, the TSI can be clocked as shown in the following figure. NOTE In the TSI chapter, these two clocks are referred to as LPOCLK and VLPOSCCLK.
Page 197: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •...
Page 198: Power-On Reset (Por)
Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V ).
Page 199 Chapter 6 Reset and Boot 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the SRSL[PIN] bit is set.
Page 200 Reset The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDSC1[LVDRE]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage rises above the low voltage detection threshold. The SRSL[LVD] bit is set following an LVD reset or POR.
Page 201 Chapter 6 Reset and Boot The MC_SRSL[LOC] bit is set to indicate the error. 6.2.2.6 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request.
Page 202: Debug Resets
Reset 6.2.3 Debug resets The following sections detail the debug resets available on the device. 6.2.3.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active.
Page 203: Boot
Chapter 6 Reset and Boot • DWT • ITM • NVIC • Crossbar bus switch • AHB-AP • Private peripheral bus 6.3 Boot This section describes the boot sequence, including sources and options. 6.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash.
Page 204: Boot Sequence
Boot reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in the following table.
Page 205 Chapter 6 Reset and Boot 4. The RESET pin is released, but the system reset of internal logic continues to be held until the Flash Controller finishes initialization. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming FTFL_FOPT[EZPORT_DIS].
Page 206 Boot K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 207: Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory.
Page 208 Power modes Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait - Allows peripherals to function while the core is in sleep mode, Sleep Interrupt via WFI reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked.
Page 209: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method BAT (backup The chip is powered down except for the VBAT supply. The RTC and Power-up battery only) the 32-byte VBAT register file for customer-critical data remain Sequence powered.
Page 210: Power Mode Transitions
Power mode transitions 7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes.
Page 211: Power Modes Shutdown Sequencing
Chapter 7 Power Management 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: •...
Page 212 Module Operation in Low Power Modes • powered = Memory is powered to retain contents. • low power = Flash has a low power state that retains configuration registers to support faster wakeup. • OFF = Modules are powered off; module is in reset state upon wakeup. •...
Page 213 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx FlexMemory low power low power low power low power low power low power in VLLS3, OFF in VLLS2 and VLLS1 Register files powered powered powered...
Page 214: Clock Gating
Clock Gating Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx OPAMP static TRIAMP static 12-bit DAC static static static static Human-machine interfaces GPIO wakeup wakeup static, pins OFF, pins latched latched Segment LCD wakeup wakeup wakeup...
Page 215: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits.
Page 216: Security Interactions With Other Modules
Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface.
Page 217 Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 218 Security Interactions with other Modules K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 219: Introduction
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: •...
Page 220 Introduction Cortex-M4 INTNMI Interrupts Sleep INTISR[239:0] NVIC Core SLEEPING Debug Trigger SLEEPDEEP Instr. Data Trace port (serial wire or multi-pin) TPIU AWIC MMCAU Private Peripheral Bus (internal) Table I-code bus Code bus D-code bus Matrix System bus SWJ-DP AHB-AP JTAG MDM-AP Figure 9-1.
Page 221: References
Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4 seems to be accepted) FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space.
Page 222: Jtag-To-Swd Change Sequence
The Debug Port IR==BYPASS or IDC ODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] To Test J TAGC Resources nTRST TC K TRACESWO (1’b1 = 4-pin J TAG) CJ TAG (1’b0 = 2-pin cJ TAG) TDI TDO PEN nSYS_TDO nSYS_TDI 1’b1 nTRST nSYS_TRST SWCLKTCK TC K nSYS_TC K...
Page 223: Debug Port Pin Descriptions
Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities.
Page 224: Ir Codes
JTAG status and control registers 9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation...
Page 225: Mdm-Ap Control Register
Chapter 9 Debug It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below.
Page 226 JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset.
Page 227: Mdm-Ap Status Register
Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Name Secure Description LLS, VLLSx Status Acknowledge Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits.
Page 228: Debug Resets
Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Name Description LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted.
Page 229: Ahb-Ap
Chapter 9 Debug • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command. • System POR reset Conversely the debug system is capable of generating system reset using the following mechanism: •...
Page 230: Itm
9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets.
Page 231: Coresight Embedded Trace Buffer (Etb)
Chapter 9 Debug 9.11 Coresight Embedded Trace Buffer (ETB) The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from any CoreSight-compliant component trace source with an ATB master port, such as a trace source or a trace funnel. It is included in this device to remove dependencies from the trace pin pad speed, and enable low cost trace solutions.
Page 232: Etb Counter Control
TPIU multiple sequential runs by executing code until the ETB is almost full, and halting or executing an interrupt handler to allow the buffer to be emptied, and then continuing executing code. The target halts or executes an interrupt handler when the buffer is almost full to empty the data and then the debugger runs the target again.
Page 233: Debug In Low Power Modes
Chapter 9 Debug • Sleep cycles • CPI (all instruction cycles except for the first cycle) • Interrupt overhead NOTE An event is emitted each time a counter overflows. • The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information.
Page 234: Debug Module State In Low Power Modes
Debug & Security 9.14.1 Debug Module State in Low Power Modes The following table shows the state of the debug modules in low power modes. These terms are used: • FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF.
Page 235: Signal Multiplexing And Signal Descriptions
Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.
Page 236: Port Control And Interrupt Module Features
Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details.
Page 237: Pinout
Chapter 10 Signal Multiplexing and Signal Descriptions 10.3 Pinout 10.3.1 K53 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
Page 238 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort USB0_DP USB0_DP USB0_DP USB0_DM USB0_DM USB0_DM VOUT33 VOUT33 VOUT33 VREGIN VREGIN VREGIN ADC0_DP1/ ADC0_DP1/ ADC0_DP1/ OP0_DP0 OP0_DP0 OP0_DP0 ADC0_DM1/ ADC0_DM1/ ADC0_DM1/ OP0_DM0 OP0_DM0 OP0_DM0 ADC1_DP1/ ADC1_DP1/ ADC1_DP1/ OP1_DP0/ OP1_DP0/ OP1_DP0/...
Page 239 Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort ADC1_SE1 ADC1_SE1 ADC1_SE1 TRI0_OUT/ TRI0_OUT/ TRI0_OUT/ OP1_DM2 OP1_DM2 OP1_DM2 TRI0_DM TRI0_DM TRI0_DM TRI0_DP TRI0_DP TRI0_DP TRI1_DM TRI1_DM TRI1_DM TRI1_DP TRI1_DP TRI1_DP TRI1_OUT/ TRI1_OUT/ TRI1_OUT/...
Page 240 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort PTA8 ADC0_SE1 ADC0_SE1 PTA8 FTM1_CH0 FB_AD17 FTM1_QD_ TRACE_D2 PTA9 DISABLED PTA9 FTM1_CH1 MII0_RXD3 FB_AD16 FTM1_QD_ TRACE_D1 PTA10 DISABLED PTA10 FTM2_CH0 MII0_RXD2 FB_AD15 FTM2_QD_ TRACE_D0 PTA11 DISABLED PTA11 FTM2_CH1 MII0_RXCL FB_OE_b...
Page 241 Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort PTB1 LCD_P1/ LCD_P1/ PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC FTM1_QD_ LCD_P1 ADC0_SE9/ ADC0_SE9/ /MII0_MDC ADC1_SE9/ ADC1_SE9/ TSI0_CH6 TSI0_CH6 G12 PTB2 LCD_P2/ LCD_P2/ PTB2 I2C0_SCL UART0_RT ENET0_158...
Page 242 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort TSI0_CH13 TSI0_CH13 B11 PTC1/ LCD_P21/ LCD_P21/ PTC1/ SPI0_PCS3 UART1_RT FTM0_CH0 LCD_P21 LLWU_P6 ADC0_SE1 ADC0_SE1 LLWU_P6 TSI0_CH14 TSI0_CH14 A12 PTC2 LCD_P22/ LCD_P22/ PTC2 SPI0_PCS2 UART1_CT FTM0_CH1 LCD_P22 ADC0_SE4 ADC0_SE4 CMP1_IN0/ CMP1_IN0/...
Page 243: K53 Pinouts
Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort PTC16 LCD_P36 LCD_P36 PTC16 UART3_RX ENET0_158 LCD_P36 8_TMR0 PTC17 LCD_P37 LCD_P37 PTC17 UART3_TX ENET0_158 LCD_P37 8_TMR1 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RT ENET0_158 LCD_P38 8_TMR2...
Page 244 Pinout PTE0 VLL3 PTE1 PTE2 PTC3 PTE3 PTC2 PTC1 PTC0 PTE4 PTB23 PTE5 PTB22 PTE6 PTB21 PTE7 PTB20 PTE8 PTB19 PTE9 PTB18 PTE10 PTB17 PTE11 PTB16 PTE12 PTB11 PTB10 USB0_DP PTB9 USB0_DM PTB8 VOUT33 PTB7 VREGIN PTB6 ADC0_DP1/OP0_DP0 PTB5 ADC0_DM1/OP0_DM0 PTB4 ADC1_DP1/OP1_DP0/OP1_DM1 PTB3...
Page 245: Module Signal Description Tables
Chapter 10 Signal Multiplexing and Signal Descriptions PTC8 PTC4 VCAP1 PTC3 PTC2 PTD7 PTD6 PTD5 PTD4 PTD0 PTC16 PTC12 PTD12 PTD11 PTD10 PTD3 PTC19 PTC15 PTC11 PTC7 VLL1 VCAP2 PTC1 PTC0 PTD15 PTD14 PTD13 PTD2 PTC18 PTC14 PTC10 PTC6 VLL2 VLL3 PTB23 PTB22...
Page 246: Core Modules
Module Signal Description Tables 10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal Description name JTAG_TMS JTAG_TMS/ JTAG Test Mode Selection SWD_DIO JTAG_TCLK JTAG_TCLK/ JTAG Test Clock SWD_CLK JTAG_TDI JTAG_TDI JTAG Test Data Input JTAG_TDO JTAG_TDO/ JTAG Test Data Output TRACE_SWO JTAG_TRST...
Page 247: Clock Modules
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-5. System Signal Descriptions (continued) Chip signal name Module signal Description name RESET — Reset bi-directional signal — MCU power — MCU ground Table 10-6. EWM Signal Descriptions Chip signal name Module signal Description name EWM_IN...
Page 248: Analog
Module Signal Description Tables Table 10-10. FlexBus Signal Descriptions Chip signal name Module signal Description name FB_CLKOUT FB_CLK FlexBus clock output FB_A[29:16] FB_A[29:16] In a non-multiplexed configuration, this is the address bus. FB_AD[31:0] FB_D[31:0]/ In a non-multiplexed configuration, this is the data bus. In a FB_AD[31:0] multiplexed configuration this bus is the address/data bus, FB_AD[31:0].
Page 249 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-11. ADC 0 Signal Descriptions (continued) Chip signal name Module signal Description name VSSA Analog ground Table 10-12. ADC 1 Signal Descriptions Chip signal name Module signal Description name ADC1_DP3, DADP[3:0] Differential analog channel inputs PGA1_DP, ADC1_DP[1:0] ADC1_DM3,...
Page 250: Communication Interfaces
Module Signal Description Tables Table 10-16. DAC 0 Signal Descriptions Chip signal name Module signal Description name DAC0_OUT — DAC output Table 10-17. DAC 1 Signal Descriptions Chip signal name Module signal Description name DAC1_OUT — DAC output Table 10-18. Op-Amp 0 Signal Descriptions Chip signal name Module signal Description...
Page 251 Chapter 10 Signal Multiplexing and Signal Descriptions Chip signal name Module signal name Description MII0_COL MII_COL Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. MII0_CRS MII_CRS Carrier sense. When asserted, indicates transmit or receive medium is not idle.
Page 252 Module Signal Description Tables Chip signal name Module signal name Description MII0_TXEN MII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first TXCLK following the final nibble of the frame.
Page 253 Chapter 10 Signal Multiplexing and Signal Descriptions Chip signal name Module signal name Description RMII0_TXEN RMII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first TXCLK following the final nibble of the frame.
Page 254 Module Signal Description Tables Table 10-25. I C 0 Signal Descriptions Chip signal name Module signal Description name I2C0_SCL Bidirectional serial clock line of the I C system. I2C0_SDA Bidirectional serial data line of the I C system. Table 10-26. I C 1 Signal Descriptions Chip signal name Module signal...
Page 255 Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-30. UART 3 Signal Descriptions Chip signal name Module signal Description name UART3_CTS Clear to send UART3_RTS Request to send UART3_TX Transmit data UART3_RX Receive data Table 10-31. UART 4 Signal Descriptions Chip signal name Module signal Description...
Page 256 Module Signal Description Tables Table 10-33. SDHC Signal Descriptions (continued) Chip signal name Module signal Description name SDHC0_D4 SDHC_D4 DAT4 line in 8-bit mode Not used in other modes SDHC0_D5 SDHC_D5 DAT5 line in 8-bit mode Not used in other modes SDHC0_D6 SDHC_D6 DAT6 line in 8-bit mode...
Page 257: Human-Machine Interfaces (Hmi)
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-34. I S 0 Signal Descriptions (continued) Chip signal name Module signal Description name I2S0_TX_FS STFS Serial transmit frame sync. The STFS port can be used as an input or output. The frame sync is used by the transmitter to synchronize the transfer of data.
Page 258 Module Signal Description Tables Table 10-37. Segment LCD Signal Descriptions Chip signal name Module signal Description name LCD_P[47:0] LCD_P[63:0] . 64 Configurable frontplane/backplane driver that connects directly to LCD frontplane/ the display backplane LCD_P[63:0] can operate as GPIO pins VLL[3:1] .
Page 259: Port Control And Interrupts (Port)
Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 Overview The port control and interrupt (PORT) module provides support for external interrupt, digital filtering and port control functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
Page 260: Modes Of Operation
Introduction • Selectable clock source for digital input filter with 5-bit resolution on filter size • Digital filter is functional in all digital pin muxing modes • Port control • Individual pull control registers with pullup, pulldown and pull-disable support •...
Page 261: External Signal Description
Chapter 11 Port control and interrupts (PORT) 11.2 External signal description Table 11-1. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device. 11.3 Detailed signal descriptions Table 11-2. PORTx interface-detailed signal descriptions Signal Description PORTx[31:0]...
Page 262 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_900C Pin Control Register n (PORTA_PCR3) 0000_0000h 11.4.1/268 4004_9010 Pin Control Register n (PORTA_PCR4) 0000_0000h 11.4.1/268 4004_9014 Pin Control Register n (PORTA_PCR5) 0000_0000h 11.4.1/268 4004_9018...
Page 263 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) reads zero) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 11.4.4/271 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 0000_0000h 11.4.5/272 4004_90C4...
Page 264 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A070 Pin Control Register n (PORTB_PCR28) 0000_0000h 11.4.1/268 4004_A074 Pin Control Register n (PORTB_PCR29) 0000_0000h 11.4.1/268 4004_A078 Pin Control Register n (PORTB_PCR30) 0000_0000h 11.4.1/268 4004_A07C...
Page 265 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B050 Pin Control Register n (PORTC_PCR20) 0000_0000h 11.4.1/268 4004_B054 Pin Control Register n (PORTC_PCR21) 0000_0000h 11.4.1/268 4004_B058 Pin Control Register n (PORTC_PCR22) 0000_0000h...
Page 266 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C030 Pin Control Register n (PORTD_PCR12) 0000_0000h 11.4.1/268 4004_C034 Pin Control Register n (PORTD_PCR13) 0000_0000h 11.4.1/268 4004_C038 Pin Control Register n (PORTD_PCR14) 0000_0000h 11.4.1/268 4004_C03C...
Page 267 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D010 Pin Control Register n (PORTE_PCR4) 0000_0000h 11.4.1/268 4004_D014 Pin Control Register n (PORTE_PCR5) 0000_0000h 11.4.1/268 4004_D018 Pin Control Register n (PORTE_PCR6) 0000_0000h...
Page 268: Pin Control Register N (Portx_Pcrn)
Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 11.4.4/271 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 11.4.5/272 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 11.4.6/273 4004_D0C8...
Page 269 Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 1001 Interrupt on rising edge. 1010 Interrupt on falling edge. 1011 Interrupt on either edge. 1100 Interrupt when logic one. Others Reserved. Lock Register Pin Control Register bits [15:0] are not locked. Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
Page 270: Global Pin Control Low Register (Portx_Gpclr)
Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description Slew Rate Enable Slew Rate configuration is valid in all digital pin muxing modes. Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
Page 271 Chapter 11 Port control and interrupts (PORT) 11.4.3 Global Pin Control High Register (PORTx_GPCHR) Addresses: PORTA_GPCHR is 4004_9000h base + 84h offset = 4004_9084h PORTB_GPCHR is 4004_A000h base + 84h offset = 4004_A084h PORTC_GPCHR is 4004_B000h base + 84h offset = 4004_B084h PORTD_GPCHR is 4004_C000h base + 84h offset = 4004_C084h PORTE_GPCHR is 4004_D000h base + 84h offset = 4004_D084h GPWE...
Page 272 Memory map and register definition PORTx_ISFR field descriptions Field Description 31–0 Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the bit. Configured interrupt has not been detected. Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag.
Page 273 Chapter 11 Port control and interrupts (PORT) 11.4.6 Digital Filter Clock Register (PORTx_DFCR) Addresses: PORTA_DFCR is 4004_9000h base + C4h offset = 4004_90C4h PORTB_DFCR is 4004_A000h base + C4h offset = 4004_A0C4h PORTC_DFCR is 4004_B000h base + C4h offset = 4004_B0C4h PORTD_DFCR is 4004_C000h base + C4h offset = 4004_C0C4h PORTE_DFCR is 4004_D000h base + C4h offset = 4004_D0C4h Reset...
Page 274 Functional description PORTx_DFWR field descriptions Field Description 31–5 This read-only field is reserved and always has the value zero. Reserved 4–0 Filter Length FILT The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches (in clock cycles) the digital filter absorbs for enabled digital filters.
Page 275 Chapter 11 Port control and interrupts (PORT) 11.5.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers.
Page 276 Functional description During stop mode, the interrupt status flag for any enabled interrupt (but not DMA request) will asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the low power mode. 11.5.4 Digital filter The digital filter capabilities of the PORT module are available in all digital pin muxing modes provided the PORT module is enabled.
Page 277 Chapter 12 System integration module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system integration module (SIM) provides system control and chip configuration registers. 12.1.1 Features • Configuration for system clocking •...
Page 278 Memory map and register definition • Deep sleep mode • VLLS mode 12.1.3 SIM Signal Descriptions Table 12-1. SIM Signal Descriptions Signa Description EZP_ EzPort mode select 12.1.3.1 Detailed signal description Table 12-2. SIM interface-detailed signal descriptions Signal Description EZP_CS EZPORT mode select State meaning Assertion-0 - Configure part for EZPORT...
Page 279 Chapter 12 System integration module (SIM) SIM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_7000 System Options Register 1 (SIM_SOPT1) Undefined 12.2.1/280 4004_8004 System Options Register 2 (SIM_SOPT2) 0000_1000h 12.2.2/282 4004_800C System Options Register 4 (SIM_SOPT4) 0000_0000h 12.2.3/284 4004_8010...
Page 280 Memory map and register definition 12.2.1 System Options Register 1 (SIM_SOPT1) The reset value of the SOPT1 register is as follows: Exit from POR and LVD: USBREGEN is set, USBSTBY is cleared, and OSC32KSEL is cleared. Exit from VLLS or other system reset: USBREGEN, USBSTBY and OSC32KSEL are unaffected Address: SIM_SOPT1 is 4004_7000h base + 0h offset = 4004_7000h Reserved Reset...
Page 281 Chapter 12 System integration module (SIM) SIM_SOPT1 field descriptions (continued) Field Description 22–20 This read-only field is reserved and always has the value zero. Reserved 32K oscillator clock select OSC32KSEL Selects the 32 kHz clock source (ERCLK32K) for Segment LCD, TSI, and LPTMR. This bit is reset only for POR/LVD.
Page 282 Memory map and register definition 12.2.2 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: SIM_SOPT2 is 4004_7000h base + 1004h offset = 4004_8004h SDHCSRC I2SSRC...
Page 283 Chapter 12 System integration module (SIM) SIM_SOPT2 field descriptions (continued) Field Description OSCERCLK clock External bypass clock (I2S0_CLKIN) 23–22 This read-only field is reserved and always has the value zero. Reserved 21–20 IEEE 1588 timestamp clock source select TIMESRC Selects the clock source for the Ethernet timestamp clock. Core/system clock.
Page 284 Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description If flash security is enabled, then this field affects what CPU operations can access off-chip via the FlexBus interface. This field has no effect if flash security is not enabled. All off-chip accesses (instruction and data) via the FlexBus are disallowed.
Page 285 Chapter 12 System integration module (SIM) SIM_SOPT4 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. FTM2 external clock driven by FTM_CLK0 pin. FTM2 external clock driven by FTM_CLK1 pin.
Page 286 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. FTM2_FLT0 pin CMP0 out 7–5 This read-only field is reserved and always has the value zero. Reserved FTM1 Fault 0 Select FTM1FLT0...
Page 287 Chapter 12 System integration module (SIM) 12.2.4 System Options Register 5 (SIM_SOPT5) Address: SIM_SOPT5 is 4004_7000h base + 1010h offset = 4004_8010h Reset UART1RXSRC UARTTXSRC UART0RXSRC UART0TXSRC Reset SIM_SOPT5 field descriptions Field Description 31–8 This read-only field is reserved and always has the value zero. Reserved 7–6 UART 1 receive data source select...
Page 288 Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description UART0_TX pin modulated with FTM2 channel 0 output Reserved 12.2.5 System Options Register 6 (SIM_SOPT6) The reset values of the RSTFLTEN and RSTFLTSEL bits are for power-on reset only. They are unaffected by other reset types.
Page 289 Chapter 12 System integration module (SIM) 12.2.6 System Options Register 7 (SIM_SOPT7) Address: SIM_SOPT7 is 4004_7000h base + 1018h offset = 4004_8018h Reset ADC1TRGSEL ADC0TRGSEL Reset SIM_SOPT7 field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved ADC1 alternate trigger enable ADC1ALTTRGEN...
Page 290 Memory map and register definition SIM_SOPT7 field descriptions (continued) Field Description 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 High speed comparator 2 output 0100 PIT trigger 0 0101 PIT trigger 1 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger...
Page 291 Chapter 12 System integration module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 1101 RTC seconds 1110 Low-power timer trigger 1011 Unused 12.2.7 System Device Identification Register (SIM_SDID) Address: SIM_SDID is 4004_7000h base + 1024h offset = 4004_8024h REVID FAMID PINID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes:...
Page 292 Memory map and register definition SIM_SDID field descriptions (continued) Field Description 3–0 Pincount identification PINID Specifies the pincount of the device. 0000 Reserved 0001 Reserved 0010 32-pin 0011 Reserved 0100 48-pin 0101 64-pin 0110 80-pin 0111 81-pin 1000 100-pin 1001 121-pin 1010 144-pin...
Page 293 Chapter 12 System integration module (SIM) SIM_SCGC1 field descriptions (continued) Field Description OPAMP Clock Gate Control OPAMP This bit controls the clock gate to the OPAMP module. Clock disabled Clock enabled 20–12 This read-only field is reserved and always has the value zero. Reserved UART5 Clock Gate Control UART5...
Page 294 Memory map and register definition SIM_SCGC2 field descriptions (continued) Field Description This bit controls the clock gate to the DAC0 module. Clock disabled Clock enabled 11–1 This read-only field is reserved and always has the value zero. Reserved ENET Clock Gate Control ENET This bit controls the clock gate to the ENET module.
Page 295 Chapter 12 System integration module (SIM) SIM_SCGC3 field descriptions (continued) Field Description This bit controls the clock gate to the FTM2 module. Clock disabled Clock enabled 23–18 This read-only field is reserved and always has the value zero. Reserved SDHC Clock Gate Control SDHC This bit controls the clock gate to the SDHC module.
Page 296 Memory map and register definition 12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4) Address: SIM_SCGC4 is 4004_7000h base + 1034h offset = 4004_8034h Reset Reset SIM_SCGC4 field descriptions Field Description This read-only field is reserved and always has the value zero. Reserved 30–29 This read-only field is reserved and always has the value one.
Page 297 Chapter 12 System integration module (SIM) SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled 17–14 This read-only field is reserved and always has the value zero. Reserved UART3 Clock Gate Control UART3 This bit controls the clock gate to the UART3 module. Clock disabled Clock enabled UART2 Clock Gate Control...
Page 298 Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled EWM Clock Gate Control This bit controls the clock gate to the EWM module. Clock disabled Clock enabled This read-only field is reserved and always has the value zero. Reserved 12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5) Address: SIM_SCGC5 is 4004_7000h base + 1038h offset = 4004_8038h...
Page 299 Chapter 12 System integration module (SIM) SIM_SCGC5 field descriptions (continued) Field Description Port D Clock Gate Control PORTD This bit controls the clock gate to the Port D module. Clock disabled Clock enabled Port C Clock Gate Control PORTC This bit controls the clock gate to the Port C module. Clock disabled Clock enabled Port B Clock Gate Control...
Page 300: System Clock Gating Control Register 6 (Sim_Scgc6)
Memory map and register definition 12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6) Address: SIM_SCGC6 is 4004_7000h base + 103Ch offset = 4004_803Ch Reset Reset SIM_SCGC6 field descriptions Field Description This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value one.
Page 301 Chapter 12 System integration module (SIM) SIM_SCGC6 field descriptions (continued) Field Description FTM0 Clock Gate Control FTM0 This bit controls the clock gate to the FTM0 module. Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. Clock disabled Clock enabled PDB Clock Gate Control...
Page 302: System Clock Gating Control Register 7 (Sim_Scgc7)
Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description SPI0 Clock Gate Control SPI0 This bit controls the clock gate to the SPI0 module. Clock disabled Clock enabled 11–5 This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero.
Page 303: System Clock Divider Register 1 (Sim_Clkdiv1)
Chapter 12 System integration module (SIM) SIM_SCGC7 field descriptions Field Description 31–3 This read-only field is reserved and always has the value zero. Reserved MPU Clock Gate Control This bit controls the clock gate to the MPU module. Clock disabled Clock enabled DMA Clock Gate Control This bit controls the clock gate to the DMA module.
Page 304 Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 27–24 Clock 2 output divider value OUTDIV2 This field sets the divide value for the peripheral clock.
Page 305 Chapter 12 System integration module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 19–16 Clock 4 output divider value OUTDIV4 This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT].
Page 306: System Clock Divider Register 2 (Sim_Clkdiv2)
Memory map and register definition 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2) Address: SIM_CLKDIV2 is 4004_7000h base + 1048h offset = 4004_8048h I2SDIV Reset I2SFRAC USBDIV Reset SIM_CLKDIV2 field descriptions Field Description 31–20 I2S clock divider value I2SDIV This field sets the divide value for when the fractional clock divider is used as the source for the I master clock.
Page 307: Flash Configuration Register 1 (Sim_Fcfg1)
Chapter 12 System integration module (SIM) 12.2.17 Flash Configuration Register 1 (SIM_FCFG1) For devices with FlexNVM: The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command. For devices with program flash only: The EESIZE and DEPART filelds are not applicable.
Page 308 Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 0001 Reserved 0010 4 KB 0011 2 KB 0100 1 KB 0101 512 Bytes 0110 256 Bytes 0111 128 Bytes 1000 64 Bytes 1001 32 Bytes 1010-1110 Reserved 1111 0 Bytes For devices without FlexNVM:Reserved 15–12...
Page 309: Flash Configuration Register 2 (Sim_Fcfg2)
Chapter 12 System integration module (SIM) 12.2.18 Flash Configuration Register 2 (SIM_FCFG2) Address: SIM_FCFG2 is 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 MAXADDR1 Reset Reset * Notes: • x = Undefined at reset. SIM_FCFG2 field descriptions Field Description Swap program flash SWAPPFLSH For devices without FlexNVM: Indicates that swap is active.
Page 310: Unique Identification Register High (Sim_Uidh)
Memory map and register definition SIM_FCFG2 field descriptions (continued) Field Description For devices without FlexNVM: This bit is always set. For devices with FlexNVM: Physical flash block 1 is used as FlexNVM For devices without FlexNVM: Reserved Physical flash block 1 is used as program flash This read-only field is reserved and always has the value zero.
Page 311: Unique Identification Register Mid-High (Sim_Uidmh)
Chapter 12 System integration module (SIM) 12.2.20 Unique Identification Register Mid-High (SIM_UIDMH) Address: SIM_UIDMH is 4004_7000h base + 1058h offset = 4004_8058h x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 312: Unique Identification Register Low (Sim_Uidl)
Functional description 12.2.22 Unique Identification Register Low (SIM_UIDL) Address: SIM_UIDL is 4004_7000h base + 1060h offset = 4004_8060h x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 313: Mode Controller
Chapter 13 Mode Controller 13.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section discusses the mode controller (MC) which controls power management and reset mechanisms including the various sources of resets on the device. The MC provides: •...
Page 314 Introduction 13.1.2 Modes of Operation The ARM CPU has three primary modes of operation: run, sleep, and deep sleep. The WFI instruction is used to invoke sleep and deep sleep modes. For Freescale microcontrollers, run, wait and stop are the common terminology used for the primary operating modes.
Page 315 Chapter 13 Mode Controller Table 13-1. Power modes (continued) Mode Description VLPR The Core Clock, System Clock and Bus Clocks maximum frequency is restricted to 2MHz max, Flash Clock is restricted to 1MHz. The slow IRC within the MCG must not be enabled when VLPR is entered.
Page 316 Introduction Any reset VLPW Wait VLPR Stop VLPS VLLS 3, 2, 1 Figure 13-1. Power Mode State Diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-2. Power mode transition triggers Transition # From Trigger Conditions Wait...
Page 317 Chapter 13 Mode Controller Table 13-2. Power mode transition triggers (continued) Transition # From Trigger Conditions VLPR Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1MHz. AVLP=1, Set RUNM = 10. NOTE: Poll VLPRS bit before transitioning out of VLPR mode.
Page 318 Introduction Table 13-2. Power mode transition triggers (continued) Transition # From Trigger Conditions VLPR VLLS(3,2,1) LPLLSM = (see PMCTRL register description for VLLS configuration), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, controlled in System Control Register in ARM core 13.1.2.2 Run Modes The device contains two different run modes: •...
Page 319 Chapter 13 Mode Controller • RUNM set to 10b to enter VLPR. • Flash programming/erasing is not allowed. • The slow IRC must not be enabled. • All clock monitors must be disabled before entering VLPR. While in VLPR, the regulator is slow responding and cannot handle fast load transitions. Therefore, do not change the clock frequency.
Page 320 Introduction 13.1.2.3.1 Wait Mode Wait mode is entered when the ARM core enters the sleep-now or sleep-on-exit modes. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled and clock gating to the peripheral is enabled via the SIM.
Page 321 Chapter 13 Mode Controller certain asynchronous mode peripherals are operating with the remainer of the MCU powered off. The tradeoffs depend upon the user's application, where power usage and state retention versus functional needs are weighed. The various stop modes are selected by setting the appropriate bits in the power mode protection (PMPROT) and power mode control (PMCTRL) registers.
Page 322 Introduction Register in the ARM core forces the MCU into VLPS and hardware sets the LPWUI bit set. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. On transitions from VLPR to VLPS with LPLLSM set to 000b, hardware forces LPLLSM to value of 010b.
Page 323 Chapter 13 Mode Controller 13.1.2.4.4 Very Low-Leakage Stop (VLLS3,2,1) Modes This device contains three very low leakage modes: VLLS3, VLLS2, and VLLS1. When a reference applies to all three low leakage modes, VLLS is used. All three of the VLLS modes can be entered from normal run or VLPR. The MCU enters the configured VLLS mode if: •...
Page 324: Mcu Reset
Introduction No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all the debug controls and settings to be powered off.
Page 325 Chapter 13 Mode Controller • Computer operating properly (COP) timer • Clock generator (MCG) loss of clock reset (LOC) • Low-voltage detect (LVD) • Wakeup from very low leakage stop modes, VLLSx • Software reset (SW) - by setting SYSRESETREQ bit of the NVIC's Application Interrupt and Reset Control Register •...
Page 326 Introduction 13.1.3.4 Multi-Clock Generator (MCG) Loss-of-Clock (LOC) Reset The MCG module supports an external reference clock. If the clock monitor is enabled (MCG_C6[CME] is set) and the external reference falls below a certain frequency (specified in the MCG_C2[RANGE] field), the MCU resets. If a loss of clock causes a reset, the SRSL[LOC] bit is set.
Page 327: Mode Control Memory Map/Register Definition
Chapter 13 Mode Controller 13.1.3.7 Software (SW) Reset Setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register forces a software reset on the device. A software reset resets of all major components except for debug. When the device is reset by a software reset, the SRSH[SW] bit is set. 13.1.3.8 Lock-Up Reset When the processor’s built-in system state protection hardware detects the core is locked up because of an unrecoverable exception, a lock-up reset occurs.
Page 328: System Reset Status Register High (Mc_Srsh)
Mode Control Memory Map/Register Definition MC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_E000 System Reset Status Register High (MC_SRSH) 13.2.1/328 4007_E001 System Reset Status Register Low (MC_SRSL) 13.2.2/329 4007_E002 Power Mode Protection Register (MC_PMPROT) 13.2.3/330 4007_E003 Power Mode Control Register (MC_PMCTRL)
Page 329: System Reset Status Register Low (Mc_Srsl)
Chapter 13 Mode Controller MC_SRSH field descriptions (continued) Field Description Indicates reset was caused by the ARM core indication of a LOCKUP event. Reset not caused by core LOCKUP event Reset caused by core LOCKUP event JTAG generated reset JTAG Indicates reset was caused by JTAG selection of certain IR codes (EZPORT, EXTEST, HIGHZ, and CLAMP).
Page 330: Power Mode Protection Register (Mc_Pmprot)
Mode Control Memory Map/Register Definition MC_SRSL field descriptions (continued) Field Description Reset not caused by POR Reset caused by POR External reset pin Indicates reset was caused by an active-low level on the external RESETpin. Reset not caused by external reset pin Reset caused by external reset pin Computer Operating Properly (COP) Watchdog Reset was caused by the COP watchdog timer timing out.
Page 331 Chapter 13 Mode Controller If the MCU is configured for a disallowed power mode, the MCU remains in its current power mode. For example, if in normal run (RUNM = 00, AVLP = 0) an attempt to enter VLPR using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b indicating MCU is still in normal run mode.
Page 332: Power Mode Control Register (Mc_Pmctrl)
Mode Control Memory Map/Register Definition MC_PMPROT field descriptions (continued) Field Description VLLS3 is not allowed VLLS3 is allowed Allow very low leakage stop 2 mode AVLLS2 This write once bit allows the MCU to enter very low leakage stop 2 mode (VLLS2) provided the appropriate control bits are set up in PMCTRL.
Page 333 Chapter 13 Mode Controller Address: MC_PMCTRL is 4007_E000h base + 3h offset = 4007_E003h Read LPWUI RUNM LPLLSM Write Reset MC_PMCTRL field descriptions Field Description Low Power Wake Up on Interrupt LPWUI Controls if the voltage regulator exits stop regulation when any active MCU interrupt occurs, returning the MCU to normal run mode.
Page 334 Mode Control Memory Map/Register Definition K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 335: Power Management Controller
Chapter 14 Power Management Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PMC contains the internal voltage regulator, power on reset (POR), and low voltage detect system. Mode Controller controls the PMC and its chapter contains description of all device resets, including POR.
Page 336: Lvd Reset Operation
Low-Voltage Detect (LVD) System selectable trip voltage: high (V ) or low (V ). The trip voltage is selected by the LVDH LVDL LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: •...
Page 337: Pmc Memory Map/Register Definition
Chapter 14 Power Management Controller The LVDSC2[LVWV] bits select one of four trip voltages: • Highest (V LVW4 • Two mid-levels (V and V LVW3 LVW2 • Lowest (V LVW1 14.4 PMC Memory Map/Register Definition The following table shows the registers related to the PMC. Mode Control Memory Map/Register Definition for the mode controller registers.
Page 338: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
PMC Memory Map/Register Definition Address: PMC_LVDSC1 is 4007_D000h base + 0h offset = 4007_D000h Read LVDF LVDIE LVDRE LVDV Write LVDACK Reset PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status bit indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Low-Voltage Detect Acknowledge...
Page 339 Chapter 14 Power Management Controller See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV bits. NOTE The reset value of this register depends on the reset type: • POR -- 0x00 •...
Page 340: Regulator Status And Control Register (Pmc_Regsc)
PMC Memory Map/Register Definition 14.4.3 Regulator Status and Control Register (PMC_REGSC) The power management controller contains an internal voltage regulator. The voltage regulator design uses a bandgap reference, that is also available through a buffer as input to certain internal peripherals. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation.
Page 341 Chapter 14 Power Management Controller PMC_REGSC field descriptions (continued) Field Description Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 342 PMC Memory Map/Register Definition K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 343: Low-Leakage Wake-Up Unit (Llwu)
Chapter 15 Low-leakage wake-up unit (LLWU) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 7 internal modules as a wakeup source from low-leakage power modes (LLS and VLLS).
Page 344: Features
Introduction 15.1.1 Features The LLWU module features include: • Supports up to 16 external input pins and up to 7 internal modules with individual enable bits • Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS.
Page 345: Block Diagram
Chapter 15 Low-leakage wake-up unit (LLWU) 15.1.2.2 VLLS modes The LLWU module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. In addition, a VLLS reset event can be initiated via assertion of the RESET pin. All wakeup and reset events result in VLLS exit via a reset flow. 15.1.2.3 Non-low leakage modes The LLWU is not active in all non- LLS and VLLS modes where detection and control logic are in a static state.
Page 346: Llwu Signal Descriptions
LLWU Signal Descriptions LLS/VLLS entered WUME7 LLWU_MWUF7 occurred Interrupt module Module7 interrupt flag flag detect (LLWU_M7IF) (System Error) WUME6 Internal LLWU_MWUF6 occurred Interrupt module Module6 interrupt flag module flag detect (LLWU_M6IF) sources LLWU_MWUF0 occurred Interrupt module Module0 interrupt flag flag detect (LLWU_M0IF) WUPE15 LLWU...
Page 347: Memory Map/Register Definition
Chapter 15 Low-leakage wake-up unit (LLWU) 15.3 Memory map/register definition The LLWU includes the following registers: • Five 8-bit wakeup source enable registers • Enable external pin input sources • Enable internal peripheral sources • Three 8-bit wakeup flag registers •...
Page 348: Llwu Pin Enable 2 Register (Llwu_Pe2)
Memory map/register definition Address: LLWU_PE1 is 4007_C000h base + 0h offset = 4007_C000h Read WUPE3 WUPE2 WUPE1 WUPE0 Write Reset LLWU_PE1 field descriptions Field Description 7–6 Wakeup Pin Enable for LLWU_P3 WUPE3 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 349 Chapter 15 Low-leakage wake-up unit (LLWU) NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_PE2 is 4007_C000h base + 1h offset = 4007_C001h Read WUPE7 WUPE6 WUPE5 WUPE4 Write...
Page 350: Llwu Pin Enable 3 Register (Llwu_Pe3)
Memory map/register definition 15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3) LLWU_PE3 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS).
Page 351: Llwu Pin Enable 4 Register (Llwu_Pe4)
Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4) LLWU_PE4 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12.
Page 352: Llwu Module Enable Register (Llwu_Me)
Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 1–0 Wakeup Pin Enable for LLWU_P12 WUPE12 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 353: Llwu Flag 1 Register (Llwu_F1)
Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_ME field descriptions (continued) Field Description Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 4 WUME4 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 3...
Page 354 Memory map/register definition Address: LLWU_F1 is 4007_C000h base + 5h offset = 4007_C005h Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write Reset LLWU_F1 field descriptions Field Description Wakeup Flag for LLWU_P7 WUF7 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF7.
Page 355: Llwu Flag 2 Register (Llwu_F2)
Chapter 15 Low-leakage wake-up unit (LLWU) LLWU_F1 field descriptions (continued) Field Description Wakeup Flag for LLWU_P1 WUF1 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF1. LLWU_P1 input was not a source of wakeup from LLS or VLLS mode LLWU_P1 input was a source of wakeup from LLS or VLLS mode Wakeup Flag for LLWU_P0...
Page 356 Memory map/register definition LLWU_F2 field descriptions (continued) Field Description LLWU_P15 input was not a source of wakeup from LLS or VLLS mode LLWU_P15 input was a source of wakeup from LLS or VLLS mode Wakeup Flag for LLWU_P14 WUF14 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF14.
Page 357: Llwu Flag 3 Register (Llwu_F3)
Chapter 15 Low-leakage wake-up unit (LLWU) 15.3.8 LLWU Flag 3 Register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this will be the source causing the CPU interrupt flow.
Page 358: Llwu Control And Status Register (Llwu_Cs)
Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Wakeup flag for module 4 MWUF4 Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism. Module 4 input was not a source of wakeup from LLS or VLLS mode Module 4 input was a source of wakeup from LLS or VLLS mode Wakeup flag for module 3...
Page 359: Functional Description
Chapter 15 Low-leakage wake-up unit (LLWU) Address: LLWU_CS is 4007_C000h base + 8h offset = 4007_C008h Read ACKISO FLTEP FLTR Write Reset LLWU_CS field descriptions Field Description Acknowledge Isolation ACKISO Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode.
Page 360: Lls Mode
Functional description The LLWU implements an optional 3-cycle glitch filter, based on the LPO clock, such that a detected external pin is required to stay asserted until the enabled glitch filter times out. There is also 2 additional cycles of latency due to synchronization that results in a total of 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled.
Page 361: Initialization
Chapter 15 Low-leakage wake-up unit (LLWU) In the case of a wakeup due to external pin or internal module wakeup, the I/O states are held until software clears the ACKISO bit (by writing a 1 to it). Recovery is always via a system reset flow and the MC_SRS[WAKEUP] is set indicating the low leakage mode was active prior to the last system reset flow.
Page 362 Functional description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 363: Miscellaneous Control Module (Mcm)
Chapter 16 Miscellaneous Control Module (MCM) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 16.1.1 Features The MCM includes these distinctive features: •...
Page 364: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory Map/Register Descriptions MCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar switch (AXBS) master configuration E008_000A 003Fh 16.2.2/364 (MCM_PLAMC) E008_000C SRAM arbitration and protection (MCM_SRAMAP) 0000_0000h 16.2.3/365 E008_0010 Interrupt status register (MCM_ISR) 0000_0000h 16.2.4/366 E008_0014...
Page 365: Sram Arbitration And Protection (Mcm_Sramap)
Chapter 16 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions Field Description 15–8 This read-only field is reserved and always has the value zero. Reserved 7–0 Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port. A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 16.2.3 SRAM arbitration and protection (MCM_SRAMAP)
Page 366: Interrupt Status Register (Mcm_Isr)
Memory Map/Register Descriptions MCM_SRAMAP field descriptions (continued) Field Description Special round robin (favors SRAM backoor accesses over the processor) Fixed priority. Processor has highest, backdoor has lowest Fixed priority. Backdoor has highest, processor has lowest This read-only field is reserved and always has the value zero. Reserved SRAM_U write protect SRAMUWP...
Page 367: Etb Counter Control Register (Mcm_Etbcc)
Chapter 16 Miscellaneous Control Module (MCM) MCM_ISR field descriptions (continued) Field Description Non-maskable interrupt pending If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires. No pending NMI Due to the ETB counter expiring, an NMI is pending Normal interrupt pending If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
Page 368: Etb Reload Register (Mcm_Etbrl)
Memory Map/Register Descriptions MCM_ETBCC field descriptions (continued) Field Description If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit clears the debug halt request. No effect Clears pending debug halt, NMI, or IRQ interrupt requests 2–1 Response type RSPT...
Page 369: Etb Counter Value Register (Mcm_Etbcnt)
Chapter 16 Miscellaneous Control Module (MCM) 16.2.7 ETB counter value register (MCM_ETBCNT) Address: MCM_ETBCNT is E008_0000h base + 1Ch offset = E008_001Ch COUNTER Reset MCM_ETBCNT field descriptions Field Description 31–11 This read-only field is reserved and always has the value zero. Reserved 10–0 Byte count counter value...
Page 370 Functional Description 16.3.1.2 Normal interrupt The MCM's normal interrupt is generated if any of the following are true: • MCM_ISCR[ETBI] is set, which is caused by • The ETB counter is enabled (MCM_ETBCC[CNTEN] = 1), • The ETB count expires, and •...
Page 371: Crossbar Switch (Axbs)
Chapter 17 Crossbar Switch (AXBS) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
Page 372: Memory Map / Register Definition
Memory Map / Register Definition 17.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and write- transfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode.
Page 373: Priority Registers Slave (Axbs_Prsn)
Chapter 17 Crossbar Switch (AXBS) AXBS memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_4600 Priority Registers Slave (AXBS_PRS6) 7654_3210h 17.2.1/373 4000_4610 Control Register (AXBS_CRS6) 0000_0000h 17.2.2/376 4000_4700 Priority Registers Slave (AXBS_PRS7) 7654_3210h 17.2.1/373 4000_4710...
Page 374 Memory Map / Register Definition • If the device contains less than five masters, values 000– 011 are valid and writing other values results in an error. • If the device contains n masters where n ≥ 5, values 0 to n-1 are valid and writing other values results in an error.
Page 375 Chapter 17 Crossbar Switch (AXBS) AXBS_PRSn field descriptions (continued) Field Description 22–20 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. This master has level 1, or highest, priority when accessing the slave port. This master has level 2 priority when accessing the slave port.
Page 376: Control Register (Axbs_Crsn)
Memory Map / Register Definition AXBS_PRSn field descriptions (continued) Field Description This read-only field is reserved and always has the value zero. Reserved 6–4 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. This master has level 1, or highest, priority when accessing the slave port. This master has level 2 priority when accessing the slave port.
Page 377 Chapter 17 Crossbar Switch (AXBS) AXBS_CRSn field descriptions Field Description Read only Forces the slave port’s CSRn and PRSn registers to be read-only. After set, only a hardware reset clears The slave port’s registers are writeable The slave port’s registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
Page 378: Master General Purpose Control Register (Axbs_Mgpcrn)
Memory Map / Register Definition AXBS_CRSn field descriptions (continued) Field Description Park on master port M1 Park on master port M2 Park on master port M3 Park on master port M4 Park on master port M5 Reserved Reserved 17.2.3 Master General Purpose Control Register (AXBS_MGPCRn) The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters.
Page 379: Functional Description
Chapter 17 Crossbar Switch (AXBS) AXBS_MGPCRn field descriptions (continued) Field Description Reserved Reserved Reserved 17.3 Functional Description 17.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port.
Page 380: Register Coherency
Functional Description The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave busses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port.
Page 381 Chapter 17 Crossbar Switch (AXBS) MGPCR[AULB] Lost control Lost control No arbitration Arbitration allowed No arbitration No arbitration Master-to-slave transfer 1 beat 1 beat 12 beat burst Figure 17-28. Undefined length burst example In this example, a master runs an undefined length burst and the MGPCR[AULB] bits indicate arbitration occurs after the fourth beat of the burst.
Page 382 Functional Description When a master makes a request to a slave port, the slave port checks if the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port.
Page 383: Initialization/Application Information
Chapter 17 Crossbar Switch (AXBS) Parking may continue to be used in a round-robin mode, but does not affect the round- robin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority.
Page 384 Initialization/application information K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 385: Memory Protection Unit (Mpu)
Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in the device. 18.2 Overview The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and...
Page 386 Overview Slave Port n Internal Address Phase Signals Peripheral Bus Access Region Evaluation Descriptor 0 Macro Access Region Evaluation Descriptor 1 Macro Access Region Evaluation Descriptor x Macro MPU_EARn MPU_EDRn Figure 18-1. MPU Block Diagram 18.2.2 Features The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system.
Page 387 Chapter 18 Memory Protection Unit (MPU) • Alternate programming model view of the access control permissions word • Priority given to granting permission over denying access for overlapping region descriptors • Detects access protection errors if a memory reference does not hit in any memory region, or if the reference is illegal in all hit memory regions.
Page 388 Memory Map/Register Definition MPU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_D020 Error Address Register, Slave Port n (MPU_EAR2) Undefined 18.3.2/392 4000_D024 Error Detail Register, Slave Port n (MPU_EDR2) Undefined 18.3.3/393 4000_D028 Error Address Register, Slave Port n (MPU_EAR3) Undefined...
Page 389 Chapter 18 Memory Protection Unit (MPU) MPU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_D46C Region Descriptor n, Word 3 (MPU_RGD6_WORD3) 0000_0000h 18.3.7/398 4000_D470 Region Descriptor n, Word 0 (MPU_RGD7_WORD0) 0000_0000h 18.3.4/394 4000_D474 Region Descriptor n, Word 1 (MPU_RGD7_WORD1)
Page 390 Memory Map/Register Definition MPU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Region Descriptor Alternate Access Control n 4000_D81C 0000_0000h 18.3.8/399 (MPU_RGDAAC7) Region Descriptor Alternate Access Control n 4000_D820 0000_0000h 18.3.8/399 (MPU_RGDAAC8) Region Descriptor Alternate Access Control n 4000_D824 0000_0000h...
Page 391 Chapter 18 Memory Protection Unit (MPU) MPU_CESR field descriptions (continued) Field Description 22–20 This read-only field is reserved and always has the value zero. Reserved 19–16 Hardware revision level Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module.
Page 392 Memory Map/Register Definition 18.3.2 Error Address Register, Slave Port n (MPU_EARn) When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in CESR[SPERR] set. Additional information about the faulting access is captured in the corresponding EDRn at the same time.
Page 393 Chapter 18 Memory Protection Unit (MPU) 18.3.3 Error Detail Register, Slave Port n (MPU_EDRn) When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in CESR[SPERR] is set. Information on the faulting address is captured in the corresponding EARn register at the same time.
Page 394 Memory Map/Register Definition MPU_EDRn field descriptions (continued) Field Description NOTE: All other encodings are reserved. User mode, instruction access User mode, data access Supervisor mode, instruction access Supervisor mode, data access Error read/write Indicates the access type of the faulting reference. Read Write 18.3.4 Region Descriptor n, Word 0 (MPU_RGD_WORD0)
Page 395 Chapter 18 Memory Protection Unit (MPU) 18.3.5 Region Descriptor n, Word 1 (MPU_RGD_WORD1) The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]).
Page 396 Memory Map/Register Definition Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. Addresses: 4000_D000h base + 408h offset + (16d × n), where n = 0d to 11d M2SM M3SM M3UM...
Page 397 Chapter 18 Memory Protection Unit (MPU) MPU_RGDn_WORD2 field descriptions (continued) Field Description Bus master 4 reads terminate with an access error and the read is not performed Bus master 4 reads allowed Bus master 4 write enable M4WE Bus master 4 writes terminate with an access error and the write is not performed Bus master 4 writes allowed This field is reserved.
Page 398 Memory Map/Register Definition MPU_RGDn_WORD2 field descriptions (continued) Field Description See M3UM description 18.3.7 Region Descriptor n, Word 3 (MPU_RGD_WORD3) The fourth word of the region descriptor contains the region descriptor’s valid bit. Addresses: 4000_D000h base + 40Ch offset + (16d × n), where n = 0d to 11d Reset MPU_RGDn_WORD3 field descriptions Field...
Page 399 Chapter 18 Memory Protection Unit (MPU) 18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn) Since software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. Addresses: 4000_D000h base + 800h offset + (4d ×...
Page 400 Memory Map/Register Definition MPU_RGDAACn field descriptions (continued) Field Description Bus master 5 writes terminate with an access error and the write is not performed Bus master 5 writes allowed Bus master 4 read enable. M4RE Bus master 4 reads terminate with an access error and the read is not performed Bus master 4 reads allowed Bus master 4 write enable M4WE...
Page 401 Chapter 18 Memory Protection Unit (MPU) MPU_RGDAACn field descriptions (continued) Field Description 4–3 Bus master 0 supervisor mode access control M0SM See M3SM description. 2–0 Bus master 0 user mode access control M0UM See M3UM description. 18.4 Functional Description In this section, the functional operation of the MPU is detailed, including the operation of the access evaluation macro and the handling of error-terminated bus cycles.
Page 402 Functional Description 18.4.1.1 Hit Determination To determine if the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses. The boolean equation for this portion of the hit determination is: region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) & RGDn_Word3[VLD] where addr is the current reference address, RGDn_Word0[SRTADDR] and RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word3[VLD] is...
Page 403 Chapter 18 Memory Protection Unit (MPU) 1. If the access does not hit in any region descriptor, a protection error is reported. 2. If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3.
Page 404 Application Information • Creating a new memory region—Load the appropriate region descriptor into an available RGDn, using four sequential 32-bit writes. The hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes.
Page 405 Chapter 18 Memory Protection Unit (MPU) Table 18-81. Overlapping Region Descriptor Example (continued) Region Description RGDn DMA1 DMA2 CP0 data & stack — — — CP0 → CP1 shared data — — CP1 → CP0 shared data CP1 data & stack —...
Page 406 Application Information K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 407 Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals.
Page 408 Memory map/register definition module address, transfer attributes, byte enables, and write data as inputs to the peripherals. The peripheral bridge captures read data from the peripheral interface and drives it to the crossbar switch. The register maps of the peripherals are located on 4 KB boundaries. Each peripheral is allocated one 4 KB block of the memory map.
Page 409 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_0040 Peripheral Access Control Register (AIPS0_PACRE) Undefined 19.2.3/418 4000_0044 Peripheral Access Control Register (AIPS0_PACRF) Undefined 19.2.3/418 4000_0048 Peripheral Access Control Register (AIPS0_PACRG) Undefined 19.2.3/418 4000_004C...
Page 410 Memory map/register definition NOTE At reset, the default value loaded into the MPROT[7-0] fields is device-specific. See the Chip Configuration details for the value on your particular device. Accesses to registers or register fields which correspond to master or peripheral locations which are not implemented return zeros on reads, and are ignored on writes.
Page 411 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field Description Master trusted for read MTR1 Determines whether the master is trusted for read accesses. This master is not trusted for read accesses. This master is trusted for read accesses. Master trusted for writes MTW1 Determines whether the master is trusted for write accesses.
Page 412 Memory map/register definition AIPSx_MPRA field descriptions (continued) Field Description This master is not trusted for write accesses. This master is trusted for write accesses. Master privilege level MPL3 Specifies how the privilege level of the master is determined. Accesses from this master are forced to user-mode. Accesses from this master are not forced to user-mode.
Page 413 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field Description 3–0 This read-only field is reserved and always has the value zero. Reserved 19.2.2 Peripheral Access Control Register (AIPSx_PACRn) Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels supported by the given module.
Page 414 Memory map/register definition Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119...
Page 415 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description This read-only field is reserved and always has the value zero. Reserved Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
Page 416 Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. This read-only field is reserved and always has the value zero. Reserved Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
Page 417 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates.
Page 418 Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates .
Page 419 Chapter 19 Peripheral Bridge (AIPS-Lite) NOTE The reset value of the PACRE-P depends on your device's configuration. Addresses: 4000_0000h base + 40h offset + (4d × n), where n = 0d to 11d x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 420 Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
Page 421 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description the master must be set. If not, access terminates with an error response and no peripheral access initiates. This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write protect Determines whether the peripheral allows write accesss.
Page 422 Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
Page 423 Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set.
Page 424 Functional Description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 425: Introduction
Chapter 20 Direct memory access multiplexer (DMAMUX) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 Overview The DMA Mux routes up to 63 DMA sources (called slots) to be mapped to any of the 16 DMA channels.
Page 426: Features
Introduction DMA Channel #0 DMAMUX Source #1 DMA Channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA Channel #n Trigger #z Figure 20-1. DMA MUX block diagram 20.1.2 Features The DMA channel MUX provides these features: •...
Page 427: External Signal Description
Chapter 20 Direct memory access multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place (e.g.
Page 428: Channel Configuration Register (Dmamux_Chcfgn)
Memory map/register definition DMAMUX memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_1000 Channel Configuration Register (DMAMUX_CHCFG0) 20.3.1/428 4002_1001 Channel Configuration Register (DMAMUX_CHCFG1) 20.3.1/428 4002_1002 Channel Configuration Register (DMAMUX_CHCFG2) 20.3.1/428 4002_1003 Channel Configuration Register (DMAMUX_CHCFG3) 20.3.1/428 4002_1004 Channel Configuration Register (DMAMUX_CHCFG4)
Page 429: Functional Description
Chapter 20 Direct memory access multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions Field Description DMA Channel Enable ENBL Enables the DMA channel DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
Page 430 Functional description such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. Please refer to Periodic Interrupt Timer chapter for more information on this topic. Note Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed.
Page 431 Chapter 20 Direct memory access multiplexer (DMAMUX) Peripheral Request Trigger DMA Request Figure 20-20. DMA MUX channel triggering: normal operation Once the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen.
Page 432: Dma Channels With No Triggering Capability
Functional description 20.4.2 DMA channels with no triggering capability The other channels of the DMA MUX provide the normal routing functionality as described in Modes of operation. 20.4.3 "Always enabled" DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are "always enabled".
Page 433: Initialization/Application Information
Chapter 20 Direct memory access multiplexer (DMAMUX) • Use explicit software re-activation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to re-activate the channel (by writing to the DMA registers) after every minor loop. For this option, the DMA channel should be disabled in the DMA channel MUX.
Page 434 Initialization/application information 3. Configure a timer for the desired trigger interval 4. Write 0xC5 to CHCFG2 (base address + 0x02) The following code example illustrates steps #1 and #4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);...
Page 435 Chapter 20 Direct memory access multiplexer (DMAMUX) volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);...
Page 436 Initialization/application information volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);...
Page 437: Direct Memory Access Controller (Edma)
Chapter 21 Direct Memory Access Controller (eDMA) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor.
Page 438: Block Parts
Introduction eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-1. eDMA block diagram 21.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
Page 439 Chapter 21 Direct Memory Access Controller (eDMA) Table 21-1. eDMA engine submodules Submodule Function Address path This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality.
Page 440: Features
Introduction Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled.
Page 441: Modes Of Operation
Chapter 21 Direct Memory Access Controller (eDMA) • Channel completion reported via optional interrupt requests • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller •...
Page 442 Memory map/register definition • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation.
Page 443 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) (always 21.3.11/ 4000_801E Clear Error Register (DMA_CERR) reads zero) (always 21.3.12/ 4000_801F Clear Interrupt Request Register (DMA_CINT) reads zero) 21.3.13/...
Page 444 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.16/ 4000_810E Channel n Priority Register (DMA_DCHPRI13) Undefined 21.3.16/ 4000_810F Channel n Priority Register (DMA_DCHPRI12) Undefined 21.3.17/ 4000_9000 TCD Source Address (DMA_TCD0_SADDR) Undefined 21.3.18/ 4000_9004...
Page 445 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Minor Byte Count (Minor Loop Disabled) 21.3.20/ 4000_9028 Undefined (DMA_TCD1_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 21.3.21/ 4000_9028 Undefined...
Page 446 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Destination Address Offset 21.3.25/ 4000_9054 Undefined (DMA_TCD2_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 21.3.26/ 4000_9056 Undefined Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 21.3.27/...
Page 447 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 21.3.30/ 4000_907E (Channel Linking Enabled) Undefined (DMA_TCD3_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 21.3.31/ 4000_907E (Channel Linking Disabled)
Page 448 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.19/ 4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) Undefined TCD Minor Byte Count (Minor Loop Disabled) 21.3.20/ 4000_90A8 Undefined (DMA_TCD5_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 21.3.21/ 4000_90A8 Undefined...
Page 449 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.24/ 4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) Undefined TCD Signed Destination Address Offset 21.3.25/ 4000_90D4 Undefined (DMA_TCD6_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 21.3.26/ 4000_90D6...
Page 450 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.29/ 4000_90FC TCD Control and Status (DMA_TCD7_CSR) Undefined TCD Beginning Minor Loop Link, Major Loop Count 21.3.30/ 4000_90FE (Channel Linking Enabled) Undefined (DMA_TCD7_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count...
Page 451 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.18/ 4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) Undefined 21.3.19/ 4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) Undefined TCD Minor Byte Count (Minor Loop Disabled) 21.3.20/ 4000_9128...
Page 452 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Source Address Adjustment 21.3.23/ 4000_914C Undefined (DMA_TCD10_SLAST) 21.3.24/ 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) Undefined TCD Signed Destination Address Offset 21.3.25/ 4000_9154 Undefined...
Page 453 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Destination Address Adjustment/Scatter Gather 21.3.28/ 4000_9178 Undefined Address (DMA_TCD11_DLASTSGA) 21.3.29/ 4000_917C TCD Control and Status (DMA_TCD11_CSR) Undefined TCD Beginning Minor Loop Link, Major Loop Count 21.3.30/...
Page 454 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.17/ 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) Undefined 21.3.18/ 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) Undefined 21.3.19/ 4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) Undefined TCD Minor Byte Count (Minor Loop Disabled) 21.3.20/...
Page 455 Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Minor Loop Offset (Minor Loop and Offset 21.3.22/ 4000_91C8 Undefined Enabled) (DMA_TCD14_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 21.3.23/ 4000_91CC Undefined...
Page 456: Control Register (Dma_Cr)
Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 21.3.27/ 4000_91F6 DMA_TCD15_CITER_ELINKNO Undefined TCD Last Destination Address Adjustment/Scatter Gather 21.3.28/ 4000_91F8 Undefined Address (DMA_TCD15_DLASTSGA) 21.3.29/ 4000_91FC TCD Control and Status (DMA_TCD15_CSR) Undefined TCD Beginning Minor Loop Link, Major Loop Count 21.3.30/...
Page 457 Chapter 21 Direct Memory Access Controller (eDMA) DMA_CR field descriptions (continued) Field Description Normal operation Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored.
Page 458: Error Status Register (Dma_Es)
Memory map/register definition DMA_CR field descriptions (continued) Field Description When in debug mode, the DMA continues to operate. When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. This read-only field is reserved and always has the value zero.
Page 459 Chapter 21 Direct Memory Access Controller (eDMA) DMA_ES field descriptions (continued) Field Description This read-only field is reserved and always has the value zero. Reserved Channel Priority Error No channel priority error The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique.
Page 460: Enable Request Register (Dma_Erq)
Memory map/register definition DMA_ES field descriptions (continued) Field Description Source Bus Error No source bus error The last recorded error was a bus error on a source read Destination Bus Error No destination bus error The last recorded error was a bus error on a destination write 21.3.3 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 16 implemented channels to enable the request signal for each channel.
Page 461 Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 13 ERQ13 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 12 ERQ12 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled...
Page 462: Enable Error Interrupt Register (Dma_Eei)
Memory map/register definition DMA_ERQ field descriptions (continued) Field Description The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 1 ERQ1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 0 ERQ0...
Page 463 Chapter 21 Direct Memory Access Controller (eDMA) DMA_EEI field descriptions (continued) Field Description Enable Error Interrupt 13 EEI13 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 12 EEI12 The error signal for corresponding channel does not generate an error interrupt...
Page 464: Clear Enable Error Interrupt Register (Dma_Ceei)
Memory map/register definition DMA_EEI field descriptions (continued) Field Description The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 1 EEI1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 0...
Page 465 Chapter 21 Direct Memory Access Controller (eDMA) 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set.
Page 466 Memory map/register definition 21.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared.
Page 467 Chapter 21 Direct Memory Access Controller (eDMA) 21.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set.
Page 468 Memory map/register definition 21.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared.
Page 469 Chapter 21 Direct Memory Access Controller (eDMA) 21.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set.
Page 470 Memory map/register definition 21.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared.
Page 471 Chapter 21 Direct Memory Access Controller (eDMA) 21.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared.
Page 472 Memory map/register definition The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status.
Page 473 Chapter 21 Direct Memory Access Controller (eDMA) DMA_INT field descriptions (continued) Field Description The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 10 INT10 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 9 INT9...
Page 474 Memory map/register definition 21.3.14 Error Register (DMA_ERR) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller.
Page 475 Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERR field descriptions (continued) Field Description Error In Channel 15 ERR15 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 14 ERR14 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 13...
Page 476 Memory map/register definition DMA_ERR field descriptions (continued) Field Description An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 3 ERR3 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred Error In Channel 2 ERR2...
Page 477 Chapter 21 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved Hardware Request Status Channel 15 HRS15 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present Hardware Request Status Channel 14 HRS14...
Page 478 Memory map/register definition DMA_HRS field descriptions (continued) Field Description Hardware Request Status Channel 4 HRS4 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present Hardware Request Status Channel 3 HRS3 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present...
Page 479 Chapter 21 Direct Memory Access Controller (eDMA) DMA_DCHPRIn field descriptions (continued) Field Description Channel n cannot be suspended by a higher priority channel’s service request Channel n can be temporarily suspended by the service request of a higher priority channel Disable Preempt Ability Channel n can suspend a lower priority channel Channel n cannot suspend any channel, regardless of channel priority...
Page 480 Memory map/register definition 21.3.18 TCD Signed Source Address Offset (DMA_TCD_SOFF) Addresses: 4000_8000h base + 1004h offset + (32d × n), where n = 0d to 15d Read SOFF Write Reset * Notes: • x = Undefined at reset. DMA_TCDn_SOFF field descriptions Field Description 15–0...
Page 481 Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_ATTR field descriptions (continued) Field Description 10–8 Source data transfer size SSIZE The attempted use of a Reserved encoding causes a configuration error. 8-bit 16-bit 32-bit Reserved 16-byte Reserved Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition 2–0...
Page 482 Memory map/register definition DMA_TCDn_NBYTES_MLNO field descriptions (continued) Field Description is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed.
Page 483 Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued) Field Description As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted;...
Page 484 Memory map/register definition DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description 9–0 Minor Byte Transfer Count NBYTES Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred.
Page 485 Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_DADDR field descriptions Field Description 31–0 Destination Address DADDR Memory address pointing to the destination data. 21.3.25 TCD Signed Destination Address Offset (DMA_TCD_DOFF) Addresses: 4000_8000h base + 1014h offset + (32d × n), where n = 0d to 15d Read DOFF Write...
Page 486 Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions Field Description Enable channel-to-channel linking on minor-loop complete ELINK As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 487 Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKNO field descriptions Field Description Enable channel-to-channel linking on minor-loop complete ELINK As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 488 Memory map/register definition DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else • This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes.
Page 489 Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. Channel Done DONE This flag indicates the eDMA has completed the major loop.
Page 490 Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field Description The half-point interrupt is disabled The half-point interrupt is enabled Enable an interrupt when major iteration count completes INTMAJOR If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero.
Page 491: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14–13 This read-only field is reserved and always has the value zero. Reserved 12–9 Link Channel Number LINKCH If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that...
Page 492: Functional Description
Functional description DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported.
Page 493 Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n.
Page 494 Functional description eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-290. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement.
Page 495: Error Reporting And Handling
Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA En g in e Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 21-291.
Page 496 Functional description • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled.
Page 497: Channel Preemption
Chapter 21 Direct Memory Access Controller (eDMA) loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel.
Page 498 Functional description address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 21.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: •...
Page 499 Chapter 21 Direct Memory Access Controller (eDMA) The eDMA design supports the following hardware service request sequence: Table 21-293. Hardware service request process, cycles 1–7 Cycle Description eDMA peripheral request is asserted. The eDMA peripheral request is registered locally in the eDMA module and qualified.
Page 500 Functional description Table 21-294. Hardware service request process, cycles 8–17 (continued) Cycle Description With internal peripheral With SRAM read and bus read and internal internal peripheral bus SRAM write write The next channel to be activated performs the read of the first part of its TCD from the local memory.
Page 501 Chapter 21 Direct Memory Access Controller (eDMA) 21.4.4.3 eDMA performance example Consider a system with the following characteristics: • Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase •...
Page 502: Initialization/Application Information
Initialization/application information 21.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 21.5.1 eDMA initialization A typical initialization of the eDMA has the following sequence: 1. Write the CR register if a configuration other than the default is desired. 2.
Page 503 Chapter 21 Direct Memory Access Controller (eDMA) Table 21-297. TCD Control and Status fields TCDn_CSR field Description name START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service)
Page 504: Programming Errors
Initialization/application information xADDR: (Starting address) xSIZE: (size of one Minor loop data transfer) (NBYTES in minor loop, Offset (xOFF): number of bytes added to often the same current address after each transfer value as xSIZE) (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR)
Page 505: Performing Dma Transfers
Chapter 21 Direct Memory Access Controller (eDMA) 21.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 21.5.4 Performing DMA transfers 21.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1).
Page 506 Initialization/application information 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b.
Page 507 Chapter 21 Direct Memory Access Controller (eDMA) 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCDn data from local memory to internal register file. 5.
Page 508 Initialization/application information b. Write 32-bits to location 0x2010 → first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 → second iteration of the minor loop. e.
Page 509: Monitoring Transfer Descriptor Status
Chapter 21 Direct Memory Access Controller (eDMA) Table 21-298. Modulo example (continued) Transfer Number Address 0x12345674 0x12345678 0x1234567C 0x12345670 0x12345674 21.5.5 Monitoring transfer descriptor status 21.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests.
Page 510 Initialization/application information TCDn_CSR bits Stage State START ACTIVE DONE Channel service request via hardware (peripheral request asserted) Channel is executing Channel has completed the minor loop and is idle Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit.
Page 511: Channel Linking
Chapter 21 Direct Memory Access Controller (eDMA) 21.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion.
Page 512: Dynamic Programming
Initialization/application information Table 21-299. Channel Linking Parameters Desired Link TCD Control Field Name Description Behavior Enable channel-to-channel linking on minor loop completion (current CITER[E_LINK] Link at end of iteration) Minor Loop CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration) CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion Link at end of...
Page 513 Chapter 21 Direct Memory Access Controller (eDMA) 1. Set the TCDn_CSR[MAJOR_E_LINK] bit. 2. Read back the TCDn_CSR[MAJOR_E_LINK] bit. 3. Test the TCDn_CSR[MAJOR_E_LINK] request status. a. If the bit is set, the dynamic link attempt was successful. b. If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring.
Page 514 Initialization/application information K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 515: External Watchdog Monitor (Ewm)
Chapter 22 External Watchdog Monitor (EWM) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
Page 516: Modes Of Operation
Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles.
Page 517: Block Diagram
Chapter 22 External Watchdog Monitor (EWM) 22.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 22.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. •...
Page 518: Ewm Signal Descriptions
EWM Signal Descriptions 22.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal Description EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the CTRL[ASSIN] bit. The default polarity is active-low.
Page 519: Service Register (Ewm_Serv)
Chapter 22 External Watchdog Monitor (EWM) Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000h Read INEN ASSIN EWMEN Write Reset EWM_CTRL field descriptions Field Description 7–3 This read-only field is reserved and always has the value zero. Reserved Input Enable.
Page 520: Compare Low Register (Ewm_Cmpl)
Memory Map/Register Definition 22.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error.
Page 521: Functional Description
Chapter 22 External Watchdog Monitor (EWM) EWM_CMPH field descriptions Field Description 7–0 To prevent runaway code from changing this field, software should write to this field after a CPU reset COMPAREH even if the (default) maximum service time is required. 22.4 Functional Description The following sections describe functional details of the EWM module.
Page 522: The Ewm_In Signal
Functional Description Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 22.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal.
Page 523: Ewm Refresh Mechanism
Chapter 22 External Watchdog Monitor (EWM) The EWM compare registers are used to create a service window, which is used by the CPU to service/refresh the EWM module. • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero.
Page 524 Functional Description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 525: Watchdog Timer (Wdog)
Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Some reasons for such failures are: run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences.
Page 526 Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits, resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. •...
Page 527: Functional Overview
Chapter 23 Watchdog Timer (WDOG) 23.3 Functional Overview WDOG Disable Control/Configuration Unlock Sequence bit changes N bus clk cycles after 2 Writes of data within K bus clock unlocking cycles of each other Refresh Sequence 2 writes of data within K 0xC520 bus clock cycles of each N bus clk cycles...
Page 528: Unlocking And Updating The Watchdog
Functional Overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application.
Page 529: The Watchdog Configuration Time (Wct)
Chapter 23 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to bother with frequently servicing the watchdog.
Page 530: Refreshing The Watchdog
Functional Overview Updates in the write–once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • the stop, wait, and debug mode enable bits • the standby mode enable bit •...
Page 531: Low Power Modes Of Operation
Chapter 23 Watchdog Timer (WDOG) non-time-out exception (see Generated Resets and Interrupts). You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 23.3.6 Low Power Modes of Operation • In Wait mode, if the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out.
Page 532: Testing The Watchdog
Testing the Watchdog The entry into Debug mode within WCT time after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT time. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result.
Page 533 Chapter 23 Watchdog Timer (WDOG) 23.4.2 Byte Test The byte test implements more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: Reset Value (Hardwired) Modulus Register...
Page 534: Backup Reset Generator
Backup Reset Generator Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts more details. 23.5 Backup Reset Generator The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which takes care that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system.
Page 535: Memory Map And Register Definition
Chapter 23 Watchdog Timer (WDOG) • A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. • A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence.
Page 536: Watchdog Status And Control Register High (Wdog_Stctrlh)
Memory Map and Register Definition WDOG memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 23.7.8/ 4005_200E Watchdog Unlock Register (WDOG_UNLOCK) D928h 23.7.9/ 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 0000h 23.7.10/ 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 0000h 23.7.11/...
Page 537 Chapter 23 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value.
Page 538: Watchdog Status And Control Register Low (Wdog_Stctrll)
Memory Map and Register Definition WDOG_STCTRLH field descriptions (continued) Field Description WDOG is disabled. WDOG is enabled. 23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: WDOG_STCTRLL is 4005_2000h base + 2h offset = 4005_2002h Read Reserved Write Reset WDOG_STCTRLL field descriptions Field Description Interrupt flag.
Page 539: Watchdog Time-Out Value Register Low (Wdog_Tovall)
Chapter 23 Watchdog Timer (WDOG) 23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain.
Page 540: Watchdog Window Register Low (Wdog_Winl)
Memory Map and Register Definition 23.7.6 Watchdog Window Register Low (WDOG_WINL) You must set the Window Register value lower than the Time-out Value Register. Address: WDOG_WINL is 4005_2000h base + Ah offset = 4005_200Ah Read WINLOW Write Reset WDOG_WINL field descriptions Field Description 15–0...
Page 541: Watchdog Timer Output Register High (Wdog_Tmrouth)
Chapter 23 Watchdog Timer (WDOG) WDOG_UNLOCK field descriptions Field Description 15–0 You can write the unlock sequence values to this register to make the watchdog write once registers WDOGUNLOCK writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens up a window equal in length to the WCT within which you can update the registers.
Page 542: Watchdog Reset Count Register (Wdog_Rstcnt)
Watchdog Operation with 8-bit access 23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT) Address: WDOG_RSTCNT is 4005_2000h base + 14h offset = 4005_2014h Read RSTCNT Write Reset WDOG_RSTCNT field descriptions Field Description 15–0 Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing RSTCNT 1 to the bit to be cleared, enables you to clear the contents of this register.
Page 543: General Guideline
Chapter 23 Watchdog Timer (WDOG) 23.8.1 General Guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, you must try to place the two 8-bit accesses one after the other in your code. 23.8.2 Refresh and Unlock operations with 8-bit access One exception condition that generates a reset to the system, is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and...
Page 544: Restrictions On Watchdog Operation
Restrictions on Watchdog Operation takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged.
Page 545 Chapter 23 Watchdog Timer (WDOG) • The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. •...
Page 546 Restrictions on Watchdog Operation K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 547: Multipurpose Clock Generator (Mcg)
Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL).
Page 548 Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL) • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source •...
Page 549 Chapter 24 Multipurpose Clock Generator (MCG) • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided •...
Page 550 Introduction Crystal Oscillator External Reference Clock CLKS OSCINIT PLLCLKEN MCG Crystal Oscillator Enable Detect EREFS IREFS PLLS ATMS RANGE STOP IREFSTEN Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM IRCS Internal CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock FCTRIM MCGOUTCLK MCGFLLCLK...
Page 551: Modes Of Operation
Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG Modes of Operation. 24.2 External Signal Description There are no MCG signals that connect off chip.
Page 552: Mcg Control 1 Register (Mcg_C1)
Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 —...
Page 553: Mcg Control 2 Register (Mcg_C2)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
Page 554: Mcg Control 3 Register (Mcg_C3)
Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description FLL (or PLL) is not disabled in bypass modes. FLL (or PLL) is disabled in bypass modes (lower power) Internal Reference Clock Select IRCS Selects between the fast or slow internal reference clock source. Slow internal reference clock selected.
Page 555: Mcg Control 4 Register (Mcg_C4)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.4 MCG Control 4 Register (MCG_C4) Reset values for DRST and DMX32 bits are 0. Address: MCG_C4 is 4006_4000h base + 3h offset = 4006_4003h Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset * Notes: •...
Page 556: Mcg Control 5 Register (Mcg_C5)
Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description Encoding 2 — Mid-high range. Encoding 3 — High range. 4–1 Fast Internal Reference Clock Trim Setting FCTRIM FCTRIM controls the fast internal reference clock frequency by controlling the fast internal reference clock period.
Page 557 Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description MCGPLLCLK is inactive. MCGPLLCLK is active. PLL Stop Enable PLLSTEN Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to run if it is written to 1.
Page 558: Mcg Control 6 Register (Mcg_C6)
Memory Map/Register Definition 24.3.6 MCG Control 6 Register (MCG_C6) Address: MCG_C6 is 4006_4000h base + 5h offset = 4006_4005h Read PLLS VDIV LOLIE Write Reset MCG_C6 field descriptions Field Description Loss of Lock Interrrupt Enable LOLIE Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS is set.
Page 559: Mcg Status Register (Mcg_S)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C6 field descriptions (continued) Field Description Table 24-9. PLL VCO Divide Factor (continued) 00001 01001 10001 11001 00010 01010 10010 11010 00011 01011 10011 11011 00100 01100 10100 11100 00101 01101 10101 11101 00110 01110 10110 11110...
Page 560 Memory Map/Register Definition MCG_S field descriptions (continued) Field Description While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV [4:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock.
Page 561: Mcg Auto Trim Control Register (Mcg_Atc)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.8 MCG Auto Trim Control Register (MCG_ATC) Address: MCG_ATC is 4006_4000h base + 8h offset = 4006_4008h Read ATMF ATME ATMS Write Reset MCG_ATC field descriptions Field Description Automatic Trim Machine Enable ATME Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit.
Page 562: Mcg Auto Trim Compare Value Low Register (Mcg_Atcvl)
Functional Description MCG_ATCVH field descriptions Field Description 7–0 ATM Compare Value High ATCVH Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: MCG_ATCVL is 4006_4000h base + Bh offset = 4006_400Bh Read ATCVL...
Page 563 Chapter 24 Multipurpose Clock Generator (MCG) Reset BLPE BLPI Returns to the state that was active before Entered from any state when the MCU entered Stop mode, unless a the MCU enters Stop mode Stop reset occurs while in Stop mode. Figure 24-12.
Page 564 Functional Description Table 24-14. MCG Modes of Operation Mode Description FLL Engaged Internal FLL engaged internal (FEI) is the default mode of operation and is entered when all the following (FEI) condtions occur: • C1[CLKS] bits are written to 00 •...
Page 565 Chapter 24 Multipurpose Clock Generator (MCG) Table 24-14. MCG Modes of Operation (continued) Mode Description FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 •...
Page 566 Functional Description Table 24-14. MCG Modes of Operation (continued) Mode Description Bypassed Low Power Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: Internal (BLPI)1 • C1[CLKS] bits are written to 01 • C1[IREFS] bit is written to 1 •...
Page 567: Low Power Bit Usage
Chapter 24 Multipurpose Clock Generator (MCG) 24.4.1.2 MCG Mode Switching The C1[IREFS] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the S[IREFST] bit. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed.
Page 568: External Reference Clock
Functional Description selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes.
Page 569: Mcg Pll Clock
Chapter 24 Multipurpose Clock Generator (MCG) 24.4.6 MCG PLL Clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, refer to the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK] is set.
Page 570: Initialization / Application Information
Initialization / Application Information Before the ATM can be enabled, the ATM expected count needs to get derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, the frequency of the external reference clock, and using the following formula: ATCV •...
Page 571 Chapter 24 Multipurpose Clock Generator (MCG) 2. Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source.
Page 572: Using A 32.768 Khz Reference
Initialization / Application Information • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz.
Page 573: Mcg Mode Switching
Chapter 24 Multipurpose Clock Generator (MCG) 24.5.2 Using a 32.768 kHz Reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range.
Page 574 Initialization / Application Information Table 24-15. MCGOUTCLK Frequency Calculation Options Clock Mode Note MCGOUTCLK FEI (FLL engaged internal) * F) Typical f = 20 MHz MCGOUTCLK immediately after reset. FEE (FLL engaged external) / FLL_R) *F / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) / FLL_R must be in the range of...
Page 575 Chapter 24 Multipurpose Clock Generator (MCG) • C1[CLKS] set to 2'b10 in order to select external reference clock as system clock source • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL •...
Page 576 Initialization / Application Information e. PBE: Then loop until S[LOCK] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 in order to select the output of the PLL as the system clock source.
Page 577 Chapter 24 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C BLPE MODE ? (S[LP]=1) C1 = 0x90 C2 = 0x1C (S[LP]=0) CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? CHECK S[IREFST] = 0? CHECK S[LOCK] = 1? CHECK S[CLKST] = %10?
Page 578 Initialization / Application Information 24.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK Frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.First, the code sequence will be described.
Page 579 Chapter 24 Multipurpose Clock Generator (MCG) • C1[CLKS] set to 2'b01 in order to switch the system clock to the internal reference clock. • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference.
Page 580 Initialization / Application Information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? CHECK S[CLKST] = %10 ? C1 = 0x54 ENTER CHECK BLPE MODE ? S[IREFST] = 0? C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 C2 = 0x02 BLPE MODE ?
Page 581 Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE Mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency.
Page 582 Initialization / Application Information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK S[IREFST] = 0? C2 = 0x00 C2 = 0x1C CHECK...
Page 583: Oscillator (Osc)
Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.2 Features and Modes Key features of the module are: •...
Page 584: Block Diagram
Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode.
Page 585: External Crystal / Resonator Connections
Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
Page 586: External Clock Connections
External Clock Connections XTAL EXTAL Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. XTAL EXTAL Crystal or Resonator Figure 25-4.
Page 587: Memory Map/Register Definitions
Chapter 25 Oscillator (OSC) XTAL EXTAL Clock Input Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/...
Page 588: Functional Description
Functional Description OSC_CR field descriptions (continued) Field Description External reference clock is inactive. External reference clock is enabled. This read-only field is reserved and always has the value zero. Reserved External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
Page 589: Osc Module States
Chapter 25 Oscillator (OSC) 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested &&...
Page 590: Osc Module Modes
Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 591 Chapter 25 Oscillator (OSC) Table 25-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain (1 kHz) up to f (32.768 kHz) osc_lo osc_lo Low-frequency, low-power (VLP) High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power High-frequency mode2, high-gain (8 MHz) up to f (32 MHz)
Page 592: Counter
Reset 25.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
Page 593: Low Power Modes Operation
Chapter 25 Oscillator (OSC) 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
Page 594 Interrupts K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 595: Rtc Oscillator
Chapter 26 RTC Oscillator 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 26.1.1 Features and Modes The key features of the RTC oscillator are as follows: •...
Page 596: Rtc Signal Descriptions
RTC Signal Descriptions control Amplitude clk out for RTC EXTAL32 detector XTAL32 Figure 26-1. RTC Oscillator Block Diagram 26.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins.
Page 597: External Crystal Connections
Chapter 26 RTC Oscillator 26.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 EXTAL32 Crystal or Resonator Figure 26-2. Crystal Connections 26.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers.
Page 598: Reset Overview
Reset Overview 26.6 Reset Overview There is no reset state associated with the RTC oscillator. 26.7 Interrupts The RTC oscillator does not generate any interrupts. K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 599: Flash Memory Controller (Fmc)
Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM.
Page 600: Features
Modes of operation 27.1.2 Features The FMC's features include: • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM.
Page 601: Memory Map And Register Descriptions
Chapter 27 Flash Memory Controller (FMC) 27.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM).
Page 602 Memory map and register descriptions Table 27-3. Program visible cache registers Cache Based at Contents of 32-bit read Nomenclature Nomenclature example storage offset 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way TAGVDW2S0 is the 13-bit and y denotes the set. tag and 1-bit valid for cache entry way 2, set 0.
Page 603 Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.5/ 4001_F130 Cache Tag Storage (FMC_TAGVDW1S4) 0000_0000h 27.4.5/ 4001_F134 Cache Tag Storage (FMC_TAGVDW1S5) 0000_0000h 27.4.5/ 4001_F138 Cache Tag Storage (FMC_TAGVDW1S6) 0000_0000h 27.4.5/ 4001_F13C...
Page 604 Memory map and register descriptions FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.8/ 4001_F200 Cache Data Storage (upper word) (FMC_DATAW0S0U) 0000_0000h 27.4.9/ 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 0000_0000h 27.4.8/ 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U)
Page 605 Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.10/ 4001_F250 Cache Data Storage (upper word) (FMC_DATAW1S2U) 0000_0000h 27.4.11/ 4001_F254 Cache Data Storage (lower word) (FMC_DATAW1S2L) 0000_0000h 27.4.10/ 4001_F258...
Page 606 Memory map and register descriptions FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.12/ 4001_F2A0 Cache Data Storage (upper word) (FMC_DATAW2S4U) 0000_0000h 27.4.13/ 4001_F2A4 Cache Data Storage (lower word) (FMC_DATAW2S4L) 0000_0000h 27.4.12/ 4001_F2A8 Cache Data Storage (upper word) (FMC_DATAW2S5U)
Page 607: Flash Access Protection Register (Fmc_Pfapr)
Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 27.4.14/ 4001_F2F0 Cache Data Storage (upper word) (FMC_DATAW3S6U) 0000_0000h 27.4.15/ 4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 0000_0000h 27.4.14/ 4001_F2F8...
Page 608 Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description Prefetching for this master is enabled. Prefetching for this master is disabled. Master 5 Prefetch Disable M5PFD These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master.
Page 609 Chapter 27 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field Description Only write accesses may be performed by this master. Both read and write accesses may be performed by this master. 13–12 Master 6 Access Protection M6AP[1:0] This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.
Page 610: Flash Bank 0 Control Register (Fmc_Pfb0Cr)
Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master...
Page 611 Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description 27–24 Cache Lock Way x CLCK_WAY[3:0] These bits determine if the given cache way is locked such that its contents will not be displaced by future misses. The bit setting definitions are for each bit in the field. Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23–20...
Page 612 Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description Bank 0 Data Cache Enable B0DCE This bit controls whether data references are loaded into the cache. Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable B0ICE This bit controls whether instruction fetches are loaded into the cache.
Page 613: Flash Bank 1 Control Register (Fmc_Pfb1Cr)
Chapter 27 Flash Memory Controller (FMC) 27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR) This register has a format similar to that for PFB0CR, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. Address: FMC_PFB1CR is 4001_F000h base + 8h offset = 4001_F008h B1RWSC[3:0] B1MW[1:0]...
Page 614 Memory map and register descriptions FMC_PFB1CR field descriptions (continued) Field Description Bank 1 Data Cache Enable B1DCE This bit controls whether data references are loaded into the cache. Do not cache data references. Cache data references. Bank 1 Instruction Cache Enable B1ICE This bit controls whether instruction fetches are loaded into the cache.
Page 615: Cache Tag Storage (Fmc_Tagvdw0Sn)
Chapter 27 Flash Memory Controller (FMC) 27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 616: Cache Tag Storage (Fmc_Tagvdw1Sn)
Memory map and register descriptions 27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 617: Cache Tag Storage (Fmc_Tagvdw2Sn)
Chapter 27 Flash Memory Controller (FMC) 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 618: Cache Tag Storage (Fmc_Tagvdw3Sn)
Memory map and register descriptions 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 619: Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
Chapter 27 Flash Memory Controller (FMC) 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 620 Memory map and register descriptions 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 621 Chapter 27 Flash Memory Controller (FMC) 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 622 Memory map and register descriptions 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 623 Chapter 27 Flash Memory Controller (FMC) 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 624 Memory map and register descriptions 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 625 Chapter 27 Flash Memory Controller (FMC) 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 626 Functional description 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
Page 627 Chapter 27 Flash Memory Controller (FMC) • These masters have write access to a portion of bank 1 when FlexNVM is used with FlexRAM as EEPROM. • For bank 0 and bank 1: • Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. •...
Page 628 Functional description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 629 Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FTFL module includes the following accessible memory regions: • Program flash memory for vector space and code store •...
Page 630 Introduction The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved.
Page 631 Chapter 28 Flash Memory Module (FTFL) • Section programming for faster bulk programming times • Read access to data flash memory possible while programming or erasing data in the program flash memory 28.1.1.3 Program Acceleration RAM Features • For devices with only program flash memory: RAM to support section programming 28.1.1.4 FlexRAM Features For devices with FlexNVM memory: •...
Page 632 Introduction • Optional interrupt generation upon flash command completion • Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 28.1.2 Block Diagram The block diagram of the FTFL module is shown in the following figure. For devices with FlexNVM feature: Interrupt Program flash Status...
Page 633 Chapter 28 Flash Memory Module (FTFL) Interrupt Program flash Status Register access registers Memory controller Control registers To MCU's flash controller Program flash Programming acceleration Figure 28-2. FTFL Block Diagram 28.1.3 Glossary Command write sequence — A series of MCU writes to the Flash FCCOB register group that initiates and controls the execution of Flash algorithms that are built into the FTFL module.
Page 634 Introduction EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field.
Page 635 Chapter 28 Flash Memory Module (FTFL) NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the FTFL module. A reduced FTFL command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used.
Page 636 Memory Map and Registers 28.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFL module. Flash Configuration Field Byte Size (Bytes) Field Description...
Page 637 Chapter 28 Flash Memory Module (FTFL) Address Range Size (Bytes) Field Description 0x00 – 0xBF Reserved 0xC0 – 0xFF Program Once Field 28.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array.
Page 638 Memory Map and Registers Table 28-1. EEPROM Data Set Size (continued) EEESPLIT EEESIZE = Unimplemented or Reserved Table 28-2. EEPROM Data Set Size Field Description Field Description This read-only bitfield is reserved and must always be written as one. Reserved EEPROM Split Factor —...
Page 639 Chapter 28 Flash Memory Module (FTFL) Table 28-3. FlexNVM Partition Code Data Flash IFR: 0x00FC DEPART = Unimplemented or Reserved Table 28-4. FlexNVM Partition Code Field Description Field Description This read-only bitfield is reserved and must always be written as one. Reserved FlexNVM Partition Code —...
Page 640 Memory Map and Registers sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1).
Page 641 Chapter 28 Flash Memory Module (FTFL) FTFL memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 28.34.6/ 4002_0010 Program Flash Protection Registers (FTFL_FPROT3) Undefined 28.34.6/ 4002_0011 Program Flash Protection Registers (FTFL_FPROT2) Undefined 28.34.6/ 4002_0012 Program Flash Protection Registers (FTFL_FPROT1) Undefined...
Page 642 Memory Map and Registers FTFL_FSTAT field descriptions (continued) Field Description The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value.
Page 643 Chapter 28 Flash Memory Module (FTFL) The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits . The unassigned bits read as noted and are not writable. The reset values for the SWAP, PFLASH, RAMRDY, and EEERDY bits are determined during the reset sequence.
Page 644 Memory Map and Registers FTFL_FCNFG field descriptions (continued) Field Description For program flash only configurations, the SWAP flag indicates which physical program flash block is located at relative address 0x0000. The state of the SWAP flag is set by the FTFL during the reset sequence .
Page 645 Chapter 28 Flash Memory Module (FTFL) During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The Flash basis for the values is signified by X in the reset value. Address: FTFL_FSEC is 4002_0000h base + 2h offset = 4002_0002h Read KEYEN...
Page 646 Memory Map and Registers FTFL_FSEC field descriptions (continued) Field Description These bits define the security state of the MCU. In the secure state, the MCU limits access to FTFL module resources. The limitations are defined per device and are detailed in the Chip Configuration details.
Page 647 Chapter 28 Flash Memory Module (FTFL) 28.34.5 Flash Common Command Object Registers (FTFL_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB.
Page 648 Memory Map and Registers FTFL_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] Data Byte 6 Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number.
Page 649 Chapter 28 Flash Memory Module (FTFL) Addresses: FTFL_FPROT3 is 4002_0000h base + 10h offset = 4002_0010h FTFL_FPROT2 is 4002_0000h base + 11h offset = 4002_0011h FTFL_FPROT1 is 4002_0000h base + 12h offset = 4002_0012h FTFL_FPROT0 is 4002_0000h base + 13h offset = 4002_0013h Read PROT Write...
Page 650 Memory Map and Registers Address: FTFL_FEPROT is 4002_0000h base + 16h offset = 4002_0016h Read EPROT Write Reset * Notes: • x = Undefined at reset. FTFL_FEPROT field descriptions Field Description 7–0 EEPROM Region Protect EPROT For devices with program flash only: Reserved For devices with FlexNVM: Individual EEPROM regions can be protected from alteration by setting the associated EPROT bit.
Page 651 Chapter 28 Flash Memory Module (FTFL) 28.34.8 Data Flash Protection Register (FTFL_FDPROT) The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any FTFL command. Unprotected regions can be changed by both program and erase operations.
Page 652 Functional Description 28.4 Functional Description The following sections describe functional details of the FTFL module. 28.4.1 Program Flash Memory Swap For devices that only contain program flash memory: The user can configure the logical memory map of the program flash space such that either of the two physical program flash blocks can exist at relative address 0x0000.
Page 653 Chapter 28 Flash Memory Module (FTFL) • FDPROT — • For 2 data flash sizes, protects eight regions of the data flash memory as shown in the following figure FlexNVM 0x0_0000 Data flash size / 8 DPROT0 Data flash size / 8 DPROT1 Data flash size / 8 DPROT2...
Page 654 Functional Description 224KB data flash 192KB data flash 0x0_0000 0x0_0000 32KB DPROT0 32KB DPROT0 32KB DPROT1 32KB DPROT1 32KB DPROT2 32KB DPROT2 32KB DPROT3 32KB DPROT3 32KB DPROT4 32KB DPROT4 32KB DPROT5 32KB DPROT5 0x2_FFFF 32KB DPROT6 64KB 0x3_7FFF EEPROM backup 32KB EEPROM backup 0x3_FFFF...
Page 655 Chapter 28 Flash Memory Module (FTFL) 28.4.3 FlexNVM Description This section describes the FlexNVM memory. This section does not apply for devices that contain only program flash memory. 28.4.3.1 FlexNVM Block Partitioning for FlexRAM The user can configure the FlexNVM block as either: •...
Page 656 Functional Description configured for EEPROM (see Set FlexRAM Function Command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table 28-4).
Page 657 Chapter 28 Flash Memory Module (FTFL) FlexNVM Block 0 FlexNVM Block 1 Data flash 0 Data flash 1 FlexRAM EEPROM partition A EEPROM partition B EEPROM EEPROM backup A backup B Unavailable Subsystem A Subsystem B EEESPLIT = 1/8, 1/4, or 1/2 Size of EEPROM partition A = EEESIZE x EEESPLIT Data flash 0 and 1 interleaved Figure 28-32.
Page 658 Functional Description After a sector in EEPROM backup is full of EEPROM data records, EEPROM data records from the sector holding the oldest data are gradually copied over to a previously- erased EEPROM backup sector. When the sector copy completes, the EEPROM backup sector holding the oldest data is tagged for erase.
Page 659 Chapter 28 Flash Memory Module (FTFL) Figure 28-33. EEPROM backup writes to FlexRAM 28.4.4 Interrupts The FTFL module can generate interrupt requests to the MCU upon the occurrence of various FTFL events. These interrupt events and their associated status and control bits are shown in the following table.
Page 660 Flash Operation in Low-Power Modes 28.4.5 Flash Operation in Low-Power Modes 28.4.5.1 Wait Mode When the MCU enters wait mode, the FTFL module is not affected. The FTFL module can recover the MCU from wait via the command complete interrupt (see Interrupts). 28.4.5.2 Stop Mode When the MCU requests stop mode, if an FTFL command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode.
Page 661: Flash Program And Erase
Chapter 28 Flash Memory Module (FTFL) 28.4.8 Read While Write (RWW) The following simultaneous accesses are allowed for devices with FlexNVM: • The user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and FlexRAM memory space.
Page 662 Flash Operation in Low-Power Modes • The command write sequence used to set FTFL command parameters and launch execution • A description of all FTFL commands available 28.4.10.1 Command Write Sequence FTFL commands are specified using a command write sequence illustrated in Figure 28-34.
Page 663 Chapter 28 Flash Memory Module (FTFL) If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group.
Page 664 Flash Operation in Low-Power Modes START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Protection Violation Clear the old errors FPVIOL Check Write 0x30 to FSTAT register Set? Write to the FCCOB registers to load the required command parameter.
Page 665 Chapter 28 Flash Memory Module (FTFL) FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x00 Read 1s Block × × × Verify that a program flash or data flash block is erased.
Page 666 Flash Operation in Low-Power Modes FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x0B Program × × × × Program data Section from the Section Program Buffer to a program flash or data...
Page 667 Chapter 28 Flash Memory Module (FTFL) FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x44 Erase All Blocks × × × × Erase all program flash blocks, program flash 1 IFR, data flash...
Page 668 Flash Operation in Low-Power Modes FCMD Command Program Program Data flash FlexRAM Function flash 0 flash 1 (Devices (Devices (Devices with with with only FlexNVM) FlexNVM) program flash) 0x81 Set FlexRAM × Switches Function FlexRAM function between RAM and EEPROM. When switching to EEPROM, FlexNVM is not...
Page 669 Chapter 28 Flash Memory Module (FTFL) Table 28-31. FTFL Commands by Mode (continued) NVM Normal NVM Special FCMD Command Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x80 Program Partition × × × × — — 0x81 Set FlexRAM Function × × ×...
Page 670: Margin Read Commands
Flash Operation in Low-Power Modes Table 28-33. Allowed Simultaneous Memory Operations Program Flash 0 Program Flash 1 Read Program Sector Erase Read Program Sector Erase Read — Program Program — flash 0 Sector Erase — Read — Program Program — flash 1 Sector Erase —...
Page 671: Ftfl Command Description
Chapter 28 Flash Memory Module (FTFL) The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting.
Page 672 Flash Operation in Low-Power Modes 28.4.12.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified.
Page 673 Chapter 28 Flash Memory Module (FTFL) 28.4.12.2 Read 1s Section Command The Read 1s Section command checks if a section of program flash or data flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of phrases to be verified.
Page 674 Flash Operation in Low-Power Modes 28.4.12.3 Program Check Command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. Table 28-40. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x02 (PGMCHK)
Page 675 Chapter 28 Flash Memory Module (FTFL) Table 28-42. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] An invalid margin choice is supplied FSTAT[ACCERR] Either of the margin reads does not match the expected data FSTAT[MGSTAT0]...
Page 676 Flash Operation in Low-Power Modes After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range.
Page 677 Chapter 28 Flash Memory Module (FTFL) Upon clearing CCIF to launch the Program Longword command, the FTFL programs the data bytes into the flash using the supplied address. The swap indicator address in each program flash block is implicitly protected from programming. The targeted flash locations must be currently unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Longword operation.
Page 678 Flash Operation in Low-Power Modes Upon clearing CCIF to launch the Erase Flash Block command, the FTFL erases the main array of the selected flash block and verifies that it is erased. When the data flash is targeted, DEPART must be set for no EEPROM (see Table 28-4) else the Erase Flash Block command aborts setting the FSTAT[ACCERR] bit.
Page 679 Chapter 28 Flash Memory Module (FTFL) address being erased is the non-active block. If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 28-35).
Page 680 Flash Operation in Low-Power Modes i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase. 28.4.12.7.3 Aborting a Suspended Erase Flash Sector Operation The user may choose to abort a suspended Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch.
Page 681 Chapter 28 Flash Memory Module (FTFL) Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE?
Page 682 Flash Operation in Low-Power Modes 28.4.12.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash Sector Programming).
Page 683 Chapter 28 Flash Memory Module (FTFL) After the Program Section operation completes, the CCIF flag is set and normal access to the FlexRAM is restored. The contents of the section program buffer may be changed by the Program Section operation. Table 28-53.
Page 684 Flash Operation in Low-Power Modes 7. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available as EEPROM. 28.4.12.9 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, EEPROM backup records, and data flash IFR have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e.
Page 685 Chapter 28 Flash Memory Module (FTFL) Table 28-56. Read 1s All Blocks Command Error Handling (continued) Error Condition Error Bit Read-1s fails FSTAT[MGSTAT0] 28.4.12.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map Program Once...
Page 686 Flash Operation in Low-Power Modes 28.4.12.11 Program Once Command The Program Once command enables programming to a reserved 64-byte field in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read...
Page 687 Chapter 28 Flash Memory Module (FTFL) 28.4.12.12 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 28-61. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the FTFL erases all...
Page 688 Flash Operation in Low-Power Modes unsecure state and the FCNFG[RAMRDY] bit sets. The security byte in the Flash Configuration Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks...
Page 689 Chapter 28 Flash Memory Module (FTFL) FTFL module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor Access Key command fails with an access error. The CCIF flag is set after the Verify Backdoor Access Key operation completes. Table 28-64.
Page 690 Flash Operation in Low-Power Modes Table 28-65. Swap Control Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Next Swap Block Status (after any reset): 0x00 - Program flash block 0 at 0x0_0000 0X01 - Program flash block 1 at 0x0_0000 1.
Page 691 Chapter 28 Flash Memory Module (FTFL) • FCCOB6 (Current Swap Block Status) - indicates which program flash block is currently located at relative flash address 0x0_0000. • FCCOB7 (Next Swap Block Status) - indicates which program flash block will be located at relative flash address 0x0_0000 after the next reset of the FTFL module.
Page 692 Flash Operation in Low-Power Modes Table 28-66. Swap Control Command Error Handling (continued) Swap Error Condition Control Error Bit Code Any errors have been encountered during the swap determination and 1, 2, 4 FSTAT[MGSTAT0] program-verify operations Any brownouts were detected during the swap determination procedure FSTAT[MGSTAT0] 1.
Page 693 Chapter 28 Flash Memory Module (FTFL) Block0 Active States Block1 Active States Uninitialized0 0xFFFF 0xFFFF Ready0 Complete1 Reset 0xFFFF 0xFFFF 0x0000 0x0000 Update0 UpErs1 0xFF00 0xFFFF 0x0000 0xFF00 Erase Erase UpErs0 Update1 0xFF00 0x0000 0xFFFF 0xFF00 Complete0 Ready1 Reset 0x0000 0x0000 0xFFFF 0xFFFF...
Page 694 Flash Operation in Low-Power Modes Table 28-67. Swap State Report Mapping Case Swap Enable Swap Indicator Swap Indicator Swap State State MGST Active Field Code Block 0xFFFF Uninitialized 0x0000 0xFF00 0x0000 Update 0x0000 0xFF00- 0xFFFF Update-Erased 0x0000 0x0000 0xFFFF Complete 0x0000 0x0000 0xFFFF...
Page 695 Chapter 28 Flash Memory Module (FTFL) 28.4.12.14.1 Swap State Determination During the reset sequence, the state of the swap system is determined by evaluating the IFR Swap Field in the program flash 1 IFR and the swap indicators located in each of the program flash blocks at the swap indicator address stored in the IFR Swap Field.
Page 696 Flash Operation in Low-Power Modes Table 28-70. Valid EEPROM Data Set Size Codes EEPROM Data Size Code (FCCOB4) EEPROM Data Set Size (Bytes) FCCOB4[EEESPLIT] FCCOB4[EEESIZE] Subsystem A + B 4 + 28 8 + 24 16 + 16 16 + 16 8 + 56 16 + 48 32 + 32...
Page 697 Chapter 28 Flash Memory Module (FTFL) Table 28-71. Valid FlexNVM Partition Codes FlexNVM Partition Code Data flash Size (Kbytes) EEPROM backup Size (Kbytes) (FCCOB5[DEPART]) 0000 0011 0100 0101 0110 1000 1011 1100 1101 1110 1. FCCOB5[7:4] = 0000 After clearing CCIF to launch the Program Partition command, the FTFL first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data flash IFR are erased.
Page 698 Flash Operation in Low-Power Modes Table 28-72. Program Partition Command Error Handling (continued) Error Condition Error Bit FlexNVM Partition Code allocates space for EEPROM backup, but EEPROM Data Size FSTAT[ACCERR] Code allocates no FlexRAM for EEPROM FCCOB4[7:6] != 00 FSTAT[ACCERR] FCCOB5[7:4] != 0000 FSTAT[ACCERR] Any errors have been encountered during the verify operation...
Page 699: Security
Chapter 28 Flash Memory Module (FTFL) When the FlexRAM is set to function as a RAM, normal read and write accesses to the FlexRAM are available. When large sections of flash memory need to be programmed, e.g. during factory programming, the FlexRAM can be used as the Section Program Buffer for the Program Section command (see Program Section Command).
Page 700 Flash Operation in Low-Power Modes 28.4.13.1 FTFL Access by Mode and Security The following table summarizes how access to the FTFL module is affected by security and operating mode. Table 28-77. FTFL Access Summary Chip Security State Operating Mode Unsecure Secure NVM Normal Full command set...
Page 701: Reset Sequence
Chapter 28 Flash Memory Module (FTFL) 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command.
Page 702 Flash Operation in Low-Power Modes K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 703: External Bus Interface (Flexbus)
Chapter 29 External Bus Interface (FlexBus) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations.
Page 704: Features
Signal Descriptions 29.1.2 Features Key FlexBus features include: • Six independent, user-programmable chip-select signals (FB_CS[5:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals • 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed address and data buses •...
Page 705: Address And Data Buses (Fb_An, Fb_Dn, Fb_Adn)
Chapter 29 External Bus Interface (FlexBus) Table 29-1. FlexBus Signal Summary Signal Description FB_A[31:0] In a non-multiplexed configuration, this is the address bus. FB_D[31:0]/ In a non-multiplexed configuration, this is the data bus. In a multiplexed FB_AD[31:0] configuration this bus is the address/data bus, FB_AD[31:0]. In non- multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24].
Page 706: Byte Enables (Fb_Be_31_24, Fb_Be_23_16, Fb_Be_15_8, Fb_Be_7_0)
Signal Descriptions 29.2.2 Chip Selects (FB_CS[5 :0]) The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer address is within the device's address space, as defined in the base- and mask-address registers. The actual number of chip selects available depends upon the pin configuration.
Page 707: Transfer Size (Fb_Tsiz[1:0])
Chapter 29 External Bus Interface (FlexBus) 29.2.7 Transfer Size (FB_TSIZ[1:0]) For memory accesses, these signals, along with FB_TBST, indicate the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. For misaligned transfers, FB_TSIZ[1:0] indicates the size of each transfer.
Page 708: Transfer Acknowledge (Fb_Ta)
Memory Map/Register Definition Note When burst (FB_TBST = 0), transfer size is 16 bytes (FB_TSIZ[1:0] = 11) and the address is misaligned within the 16-byte boundary, the external device must be able to wrap around the address. 29.2.9 Transfer Acknowledge (FB_TA) This input signal indicates the external data transfer is complete.
Page 709 Chapter 29 External Bus Interface (FlexBus) Note You must set CSMR0[V] before the chip select registers take effect. A bus error occurs when writing to reserved register locations. FB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex)
Page 710: Chip Select Address Register (Fb_Csarn)
Memory Map/Register Definition FB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 29.3.2/ 4000_C040 Chip select mask register (FB_CSMR5) 0000_0000h 29.3.3/ 4000_C044 Chip select control register (FB_CSCR5) 0000_0000h 29.3.4/ 4000_C060 Chip select port multiplexing control register (FB_CSPMCR) 0000_0000h 29.3.1 Chip select address register (FB_CSARn) The CSARn registers specify the chip-select base addresses.
Page 711: Chip Select Mask Register (Fb_Csmrn)
Chapter 29 External Bus Interface (FlexBus) 29.3.2 Chip select mask register (FB_CSMRn) CSMRn registers specify the address mask and allowable access types for the respective chip-selects. Addresses: FB_CSMR0 is 4000_C000h base + 4h offset = 4000_C004h FB_CSMR1 is 4000_C000h base + 10h offset = 4000_C010h FB_CSMR2 is 4000_C000h base + 1Ch offset = 4000_C01Ch FB_CSMR3 is 4000_C000h base + 28h offset = 4000_C028h FB_CSMR4 is 4000_C000h base + 34h offset = 4000_C034h...
Page 712: Chip Select Control Register (Fb_Cscrn)
Memory Map/Register Definition FB_CSMRn field descriptions (continued) Field Description Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip- selects do not assert until V bit is set (except for FB_CS0, which acts as the global chip-select). Reset clears each CSMRn[V].
Page 713 Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description (CSCRn[WS]). If the SWSEN bit is cleared, the WS value is used for all burst transfers and this field is ignored. 25–24 This read-only field is reserved and always has the value zero. Reserved Secondary wait state enable SWSEN...
Page 714 Memory Map/Register Definition FB_CSCRn field descriptions (continued) Field Description The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If AA is reserved, FB_TA must be asserted by the external system regardless of the number of generated wait states.
Page 715: Chip Select Port Multiplexing Control Register (Fb_Cspmcr)
Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description Specifies whether burst writes are used for memory associated with each FB_CSn. Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. Enables burst write of data larger than the specified port size, including longword writes to 8 and 16- bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
Page 716: Functional Description
Functional Description FB_CSPMCR field descriptions (continued) Field Description 23–20 FlexBus signal group 3 multiplex control GROUP3 Controls the multiplexing of the FB_CS5, FB_TSIZ1, and FB_BE_23_16 signals. 0000 FB_CS5 0001 FB_TSIZ1 0010 FB_BE_23_16 Else Reserved 19–16 FlexBus signal group 4 multiplex control GROUP4 Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals.
Page 717 Chapter 29 External Bus Interface (FlexBus) • Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. • Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. 29.4.1.1 General Chip-Select Operation When a bus cycle is routed to the FlexBus, the device first compares its address with the base address and mask configurations programmed for chip-selects 0 to 5 (configured in...
Page 718: Data Transfer Operation
Functional Description No bit ordering is required when connecting address and data lines to the FB_AD bus. For example, a full 16-bit address/16-bit data device connects its addr[15:0] to FB_AD[16:1] and data[15:0] to FB_AD[31:16]. See Data Byte Alignment and Physical Connections for a graphical connection.
Page 719: Address/Data Bus Multiplexing
Chapter 29 External Bus Interface (FlexBus) Byte Select FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 External FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0] Data Bus 32-Bit Port B yte 3 Byte 2 Byte 1 Byte 0 Memory 16-Bit Port Byte 1 Byte 0 Driven with Memory address values Byte 3 Byte 2...
Page 720: Bus Cycle Execution
Functional Description Table 29-27. FlexBus Multiplexed Operating Modes for CSCRn[BLS]=0 FB_AD Port Size and Phase [31:24] [23:16] [15:8] [7:0] Address phase Address Data phase Data Address phase Address Data phase Data Address Address phase Address Data phase Data Address Table 29-28. FlexBus Multiplexed Operating Modes for CSCRn[BLS]=1 FB_AD Port Size and Phase [31:24]...
Page 721 Chapter 29 External Bus Interface (FlexBus) 4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. 29.4.5.1 Data Transfer Cycle States An on-chip state machine controls the data-transfer operation in the device.
Page 722: Flexbus Timing Examples
Functional Description 29.4.6 FlexBus Timing Examples Note The timing diagrams throughout this section use signal names that may not be included on your particular device. Ignore these extraneous signals. Note Throughout this section: • FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus •...
Page 723 Chapter 29 External Bus Interface (FlexBus) Note FB_TA does not have to be driven by the external device for internally-terminated bus cycles. Note The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses.
Page 724 Functional Description FlexBus External Memory/Peripheral 1. Set FB_R/W to write. 2. Place address on the external address signals. 3. Assert transfer start. 1. Decode address. 1. Negate transfer start. 2. Assert FB_CSn. 3. Drive data. 1. Select the appropriate slave device. 1.
Page 725 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-29. Basic Write-Bus Cycle 29.4.6.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. 29.4.6.3.1 Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait States The following figure illustrates the basic byte read transfer to an 8-bit device with no wait states:...
Page 726 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 01 Figure 29-30. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24].
Page 727 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=01 Figure 29-31. Single Byte-Write Transfer 29.4.6.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States The following figure illustrates the basic word read transfer to a 16-bit device with no wait states.
Page 728 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 10 Figure 29-32. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16].
Page 729 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 29-33. Single Word-Write Transfer 29.4.6.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device.
Page 730 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-34. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 731 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=00 Figure 29-35. Longword-Write Transfer 29.4.6.4 Timing Variations The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data.
Page 732 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-36. Basic Read-Bus Cycle (No Wait States) K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 733 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-37. Basic Write-Bus Cycle (No Wait States) If wait states are used, the S1 state repeats continuously until the the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.
Page 734 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-38. Read-Bus Cycle (One Wait State) K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 735 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-39. Write-Bus Cycle (One Wait State) 29.4.6.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis.
Page 736 Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-40. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 737 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-41. Write-Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, a programmable address hold option for each chip select exists.
Page 738 Functional Description FB_CLK Address FB_A[Y] FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-42. Read Cycle with Two-Clock Address Hold (No Wait States) K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 739 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-43. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. K53 Sub-Family Reference Manual, Rev.
Page 740: Burst Cycles
Functional Description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-44. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 29.4.7 Burst Cycles The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination.
Page 741 Chapter 29 External Bus Interface (FlexBus) Table 29-30. Transfer Size and Port Size Translation Burst-Inhibited: Number of Transfers Port Size PS[1:0] Transfer Size FB_TSIZ[1:0] Burst Enabled: Number of Beats 01 (8-bit) 10 (16-bits) 00 (32-bits) 11 (16 bytes) 1x (16-bit) 00 (32 bits) 11 (16 bytes) 00 (32-bit)
Page 742 Functional Description FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 11 Figure 29-45. 32-bit-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States) The following figure shows a 32-bit write to an 8-bit device with burst enabled.
Page 743 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-46. 32-bit-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States) The following figure shows a 32-bit read from an 8-bit device with burst inhibited.
Page 744 Functional Description FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Data Add+2 Add+3 Add+1 Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OE FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 01 TSIZ = 00 Figure 29-47. 32-bit-Read Burst-Inhibited from 8-Bit Port (No Wait States) The following figure shows a 32-bit write to an 8-bit device with burst inhibited.
Page 745 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Data Add+2 Add+3 Add+1 Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 01 TSIZ = 00 Figure 29-48. 32-bit-Write Burst-Inhibited to 8-Bit Port (No Wait States) The following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats.
Page 746 Functional Description FB_CLK FB_A[Y] Address Add+3 Add+1 Add+2 FB_D[X] Address Data Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-49. 32-bit-Read Burst from 8-Bit Port 3-2-2-2 (One Wait State) The following figure illustrates a write burst transfer with one wait state.
Page 747 Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-50. 32-bit-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State) If address setup and hold are used, only the first and last beat of the burst cycle are affected.
Page 748 Functional Description FB_CLK FB_A[Y] Address Add+1 Add+2 Add+3 FB_D[X] Address Data Data Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=11 Figure 29-51. 32-bit-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold) The following figure shows a write cycle with one clock of address setup and address hold.
Page 749: Extended Transfer Start/Address Latch Enable
Chapter 29 External Bus Interface (FlexBus) 29.4.8 Extended Transfer Start/Address Latch Enable The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address and attributes are valid. By default, the FB_TS/FB_ALE signal asserts for a single bus clock cycle. When CSCRn[EXTS] is set, the FB_TS/FB_ALE signal asserts and remain asserted until the first positive clock edge after FB_CSn asserts.
Page 750: Initialization/Application Information
Initialization/Application Information The types of accesses that cause the access to terminate with a bus error are: • Writes to write-protected region • Address with no hit to any chip select • Address with hits to multiple chip selects • Writes to reserved addresses in the memory map •...
Page 751: Overview
Chapter 30 EzPort 30.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. EzPort is a serial flash programming interface that allows In-System Programming (ISP) of flash memory contents on a 32 bit general purpose micro-controller. Memory contents can be read, erased and programmed from off-chip in a compatible format to many stand- alone flash memory chips, without necessitating the removal of the micro-controller from the system.
Page 752: Features
Overview EzPort Enabled EZP_CS EZP_CK Flash EzPort Controller EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Micro-controller Core Figure 30-1. EzPort Block Diagram 30.1.2 Features The EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. •...
Page 753: External Signal Description
Chapter 30 EzPort The EzPort provides a simple interface to connect an external device to the flash memory on board a 32 bit micro-controller. The interface itself is compatible with the SPI interface (with the EzPort operating as a slave) running in either of the two following modes with data transmitted most significant bit first: •...
Page 754: Ezport Serial Data In (Ezp_D)
Command Definition 30.2.2 EzPort Chip Select (EZP_CS) Chip select for signalling the start and end of serial transfers. If EZP_CS is asserted during and when the micro-controller's reset out signal is negated, then EzPort is enabled out of reset; otherwise it is disabled. After EzPort is enabled, asserting EZP_CS commences a serial data transfer, which continues until EZP_CS is negated again.
Page 755: Command Descriptions
Chapter 30 EzPort Table 30-2. EzPort Commands (continued) Address Accepted when Command Description Code Data Bytes Bytes secure? RESET Reset Chip 0xB9 WRFCCOB Write FCCOB Registers 0xBA Read FCCOB registers at high FAST_RDFCCOB 0xBB 1 - 12 speed WRFLEXRAM Write FlexRAM 0xBC RDFLEXRAM Read FlexRAM...
Page 756 Command Definition Table 30-3. EzPort Status Register FLEXRAM BEDIS Reset: 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects FlexNVM flash partitioning. If FlexNVM flash has been paritioned for EEPROM, this bit is set immediately after reset.
Page 757 Chapter 30 EzPort Table 30-4. EzPort Status Register Field Descriptions (continued) Field Description Write error flag Status flag that indicates if there has been an error while executing a write command (SP, SE, BE, WRFCCOB, or WRFLEXRAM). The WEF flag will set if either the Flash Access Error Flag (ACCERR) or the Flash Protection Violation Flag (FPVIOL) or the Memory Controller Command Completion Status Flag (MGSTAT0) inside the flash memory is set at the completion of the write command.
Page 758 Command Definition 30.3.1.6 Section Program The Section Program (SP) command programs up to one section of flash memory which has previously been erased. A section is defined as the smaller of the flash sector size or half the size of the FlexRAM/Programming Acceleration RAM. The starting address of the memory to program is sent after the command word and must be a 64-bit aligned address (the three LSBs must be zero).
Page 759 Chapter 30 EzPort 30.3.1.8 Bulk Erase The Bulk Erase (BE) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. Flash security is disabled upon successful completion of the BE command. Attempts to issue a BE command while the BEDIS and FS bits are set results in the WEF flag being set in the EzPort status register.
Page 760 Command Definition 30.3.1.11 Read FCCOB Registers at High Speed The Read FCCOB Registers at High Speed (FAST_RDFCCOB) command allows the user to read the contents of the flash common command object registers. After receiving the command, EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B.
Page 761: Flash Memory Map For Ezport Access
Chapter 30 EzPort The Read FlexRAM (RDFLEXRAM) command returns data from the FlexRAM. If the FlexRAM is configured for EEPROM operation, the RDFLEXRAM command can effectively be used to read data from EEPROM-flash memory. Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing.
Page 762 Flash Memory Map for EzPort Access Table 30-5. Flash Memory Map for EzPort Access (continued) Valid Start Address Size Flash block Valid Commands See device's Chip 0x0080_0000 FlexNVM READ, FAST_READ, SP, SE, BE Configuration details See device's Chip RDFLEXRAM, FAST_RDFLEXRAM, 0x0000_0000 FlexRAM Configuration details...
Page 763 Chapter 31 Cyclic redundancy check (CRC) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard.
Page 764 Memory map and register descriptions 31.1.2 Block diagram This is a block diagram of the CRC. FXOR TOTR CRC Data Register [31:24] CRC Data Register Seed Reverse [23:16] [31:24] Logic [15:8] Reverse [23:16] CRC Data [7:0] Logic Logic [15:8] [7:0] Checksum CRC Polynomial CRC Engine...
Page 765 Chapter 31 Cyclic redundancy check (CRC) CRC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) FFFF_ 31.2.1/ 4003_2000 CRC Data Register (CRC_CRC) FFFFh 31.2.2/ 4003_2004 CRC Polynomial Register (CRC_GPOLY) 0000_1021h 31.2.3/ 4003_2008 CRC Control Register (CRC_CTRL) 0000_0000h 31.2.1 CRC Data Register (CRC_CRC) The CRC data register contains the value of the seed, data, and checksum.
Page 766 Memory map and register descriptions CRC_CRC field descriptions (continued) Field Description 23–16 CRC High Lower Byte In 16-bit CRC mode (the CTRL[TCRC] bit is 0), this field is not used for programming a seed value. In 32- bit CRC mode (the CTRL[TCRC] bit is 1), values written to this field are part of the seed value when the CTRL[WAS] bit is 1.
Page 767 Chapter 31 Cyclic redundancy check (CRC) 31.2.3 CRC Control Register (CRC_CTRL) This register controls the configuration and working of the CRC module. Appropriate bits must be set before starting a new CRC calculation. A new CRC calculation is initialized by asserting the CTRL[WAS] bit and then writing the seed into the CRC data register. Address: CRC_CTRL is 4003_2000h base + 8h offset = 4003_2008h Reset CRC_CTRL field descriptions...
Page 768 Functional description CRC_CTRL field descriptions (continued) Field Description Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. 23–0 This read-only field is reserved and always has the value zero. Reserved 31.3 Functional description 31.3.1 CRC initialization/re-initialization To enable the CRC calculation, the user must program the WAS, POLYNOMIAL, and necessary parameters for transpose and CRC result inversion in the applicable registers.
Page 769 Chapter 31 Cyclic redundancy check (CRC) 5. Write a 16-bit seed to CRC[LU:LL]. CRC[HU:HL] are not used. 6. Clear the CTRL[WAS] bit to start writing data values. 7. Write data values into CRC[HU:HL:LU:LL]. A CRC is computed on every data value write, and the intermediate CRC result is stored back into CRC[LU:LL].
Page 770 Functional description 31.3.3.1 Types of transpose The CRC module provides several types of transpose functions to flip the bits and/or bytes (for both writing input data and reading the CRC result, separately using the CTRL[TOT] or CTRL[TOTR] fields) according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register.
Page 771 Chapter 31 Cyclic redundancy check (CRC) Figure 31-7. Transpose type 11 NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only.
Page 772 Functional description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 773 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Memory-Mapped Cryptographic Acceleration Unit (MMCAU) is a coprocessor that is connected to the processor's Private Peripheral Bus (PPB). It supports the hardware implementation of a set of specialized operations to improve the throughput of software- based security encryption/decryption operations and message digest functions.
Page 774 MMCAU Block Diagram Private Peripheral Bus (PPB) PADDR PWDATA PRDATA MMCAU Translator 4-entry FIFO & Control Address Data RESULT Control logic CAU_STR Figure 32-1. MMCAU Block Diagram Table 32-1. MMCAU parts table Item Description Provides the bridge between the private APB interface and the CAU module. Passes memory- Translator submodule mapped commands and data on the APB to/from the CAU Contains commands and input operands plus the associated control captured from the PPB...
Page 775 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) CA0-CA3 DES / AES Row Result Register File Hash Operand1 Command Datapath Decode Control Figure 32-2. Top Level CAU Block Diagram 32.3 Overview As the name suggests, the MMCAU provides a mechanism for memory-mapped register reads and writes to be transformed into specific commands and operands sent to the CAU coprocessor.
Page 776 Features This partitioning of functions is key to minimizing size of the MMCAU while maintaining a high level of throughput. Using software for some functions also simplifies the MMCAU design. The CAU implements a set of coprocessor commands that operate on a register file of 32-bit registers.
Page 777 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) Code Register SHA-1 SHA-256 General — — — purpose register 5 (CA5) General — — — — purpose register 6 (CA6) General — — — — purpose register 7 (CA7) General — — —...
Page 778 Memory Map/Register Definition CAU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 32.5.3/ E008_1007 General Purpose Register (CAU_CA5) 0000_0000h 32.5.3/ E008_1008 General Purpose Register (CAU_CA6) 0000_0000h 32.5.3/ E008_1009 General Purpose Register (CAU_CA7) 0000_0000h 32.5.3/ E008_100A...
Page 779 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 32.5.2 Accumulator (CAU_CAA) Commands use the CAU accumulator for storage of results and as an operand for the cryptographic algorithms. Address: CAU_CAA is E008_1000h base + 1h offset = E008_1001h Reset CAU_CAA field descriptions Field Description 31–0...
Page 780 Functional Description 32.6 Functional Description This section discusses the programming model and operation of the MMCAU. 32.6.1 MMCAU Programming Model The 4-entry FIFO is indirectly mapped into a 4-KByte address space associated with the MMCAU (located at byte addresses 0xE008_1000 - 0xE008_1FFF on this device). This address space is effectively split into 2 equal regions: •...
Page 781 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) Direct loads Indirect load/stores (commands only) (commands & operands) 0xE008_1000 0xE008_1800 CNOP, ADRA, MVRA, MVAR, AESS, AESIS, AESR, AESIR, DESR, DESK, HASH, SHS, 0xE008_1840 MDS, SHS2, and ILL commands LDR CAx 0xE008_1868 0xE008_0040 0xE008_1880 STR CAx 0xE008_18A8...
Page 782 Functional Description 32.6.1.2 Indirect Loads For CAU load operations requiring a 32-bit input operand, the address contains the 9-bit opcode to be passed to the MMCAU while the data is the 32-bit operand. Specifically, the MMCAU address and data for these indirect writes is defined as: CAU_CMD MMCAU base address Write address...
Page 783 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) • Any MMCAU reference using a non-0-modulo-4 byte address (addr[1:0] ≠ 00) generates an error termination. • For MMCAU writes: • Only the first 64 bytes of the 2-Kbyte direct write address space can be referenced.
Page 784 Functional Description Value of bits 31, 20, and 9 Number of commands included All other combinations of bits 31, 20, and 9 are illegal and generate an error termination. 32.6.3 CAU Commands The CAU supports the commands shown in the following table. All other encodings are reserved.
Page 785 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) Table 32-15. CAU Commands (continued) Command Type Description Operation Name Indirect load AESIC AES Inv Column Op 0x0D InvMixColumns(CAx^Op1) → Direct load AESR AES Shift Rows 0x0E0 ShiftRows(CA0-CA3) → CA0-CA3 Direct load AESIR AES Inv Shift Rows 0x0F0 InvShiftRows(CA0-CA3)→...
Page 786 Functional Description 32.6.3.3 Store Register (STR) The STR command returns the value of CAx specified in the read address to the destination specified as read data. 32.6.3.4 Add to Register (ADR) The ADR command adds the source operand specified by the write data to CAx and stores the result in CAx.
Page 787 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 32.6.3.9 Move Register to Accumulator (MVRA) The MVRA command moves the value from the source register CAx to the destination register CAA. 32.6.3.10 Move Accumulator to Register (MVAR) The MVAR command moves the value from source register CAA to the destination register CAx.
Page 788 Functional Description Table 32-17. AESR Command Example Register Before After 0x0102_0304 0x0106_0B00 0x0506_0708 0x050A_0F04 0x090A_0B0C 0x090E_0308 0x0D0E_0F00 0x0D02_070C 32.6.3.16 AES Inverse Shift Rows (AESIR) The AESIR command performs the AES inverse shift rows operation on registers CA0, CA1, CA2 and CA3. This table shows an example. Table 32-18.
Page 789 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 32.6.3.18 DES Key Setup (DESK) The DESK command performs the initial key transformation (permuted choice 1) defined by the DES algorithm on CA0 and CA1 with CA0 containing bits 1–32 of the key and CA1 containing bits 33–64 of the key .
Page 790 Functional Description 32.6.3.20 Secure Hash Shift (SHS) The SHS command does a set of parallel register-to-register move and shift operations for implementing SHA-1. The following source and destination assignments are made: Register Value prior to command Value after command executes CA1<<<30 CAA<<<5 32.6.3.21 Message Digest Shift (MDS)
Page 791 Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 32.6.3.23 Illegal Command (ILL) The ILL command is a specific illegal command that sets CASR[IC]. All other illegal commands are reserved for use in future implementations. 32.7 Application/Initialization Information This section discusses how to initialize and use the MMCAU. 32.7.1 Code Example A code fragment is shown below as an example of how the MMCAU is used.
Page 792 Application/Initialization Information .set CASR,0x0 .set CAA,0x1 .set CA0,0x2 .set CA1,0x3 .set CA2,0x4 .set CA3,0x5 .set CA4,0x6 .set CA5,0x7 .set CA6,0x8 .set CA7,0x9 .set CA8,0xA ; CAU Commands .set CNOP,0x000 .set LDR,0x010 .set STR,0x020 .set ADR,0x030 .set RADR,0x040 .set ADRA,0x050 .set XOR,0x060 .set ROTL,0x070 .set MVRA,0x080 .set MVAR,0x090...
Page 793 Chapter 33 Random Number Generator (RNGB) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The purpose of the RNGB is to generate cryptographically strong random data. It uses a true random number generator (TRNG) and a pseudo-random number generator (PRNG) to achieve true randomness and cryptographic strength.
Page 794 Modes of Operation Random Number Generator XSEED PRNG TRNG Generator Reseed Registers & Internal Bus Interface Internal Bus Figure 33-1. RNG Block Diagram 33.1.2 Features The RNG includes these distinctive features: • National Institute of Standards and Technology (NIST)-approved pseudo-random number generator •...
Page 795 Chapter 33 Random Number Generator (RNGB) 33.2.2 Seed Generation Mode During seed generation, the RNGB adds entropy generated in the TRNG to the 256-bit XKEY register. The PRNG algorithm executes 20,000 times sampling the entropy from the TRNG to create an initial seed for random number generation. At the same time, the TRNG runs simple statistical tests on its output.
Page 796 Memory Map/Register Definition RNG memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 33.3.1/ 400A_0000 RNGB Version ID Register (RNG_VER) 1000_0280h 33.3.2/ 400A_0004 RNGB Command Register (RNG_CMD) 0000_0000h 33.3.3/ 400A_0008 RNGB Control Register (RNG_CR) 0000_0000h 33.3.4/ 400A_000C...
Page 797 Chapter 33 Random Number Generator (RNGB) 33.3.2 RNGB Command Register (RNG_CMD) RNG_CMD controls the RNG's operating modes and interrupt status. Address: RNG_CMD is 400A_0000h base + 4h offset = 400A_0004h Reset RNG_CMD field descriptions Field Description 31–7 This read-only field is reserved and always has the value zero. Reserved Reserved, must be cleared.
Page 798 Memory Map/Register Definition RNG_CMD field descriptions (continued) Field Description • When RNG_SR[BUSY] is cleared, or • If set simultaneously with GS, self test takes precedence and is completed first. When self test completes, this bit automatically clears and an interrupt may be generated if all requested operations are complete.
Page 799 Chapter 33 Random Number Generator (RNGB) RNG_CR field descriptions (continued) Field Description Mask done interrupt. MASKDONE Masks interrupts generated upon completion of seed and self test modes. The status of these jobs can be viewed by: • Reading RNG_SR and viewing the seed done and self test done bits (RNG_SR[SDN, STDN]) •...
Page 800 Memory Map/Register Definition 33.3.4 RNGB Status Register (RNG_SR) The RNGBSR is a read-only register which reflects the internal status of the RNGB. Address: RNG_SR is 400A_0000h base + Ch offset = 400A_000Ch STATPF ST_PF Reset FIFO_SIZE FIFO_LVL Reset RNG_SR field descriptions Field Description 31–24...
Page 801 Chapter 33 Random Number Generator (RNGB) RNG_SR field descriptions (continued) Field Description Error. Indicates an error was detected in the RNGB. Read the RNG_ESR register for details. No error. Error detected. 15–12 FIFO size. FIFO_SIZE Size of the FIFO, and maximum possible FIFO level. The bits should be interpreted as an integer. This value is set to five on the default version of RNGB.
Page 802 Memory Map/Register Definition RNG_SR field descriptions (continued) Field Description Reflects the current state of RNGB. If RNGB is currently seeding, generating the next seed, creating a new random number, or performing a self test, this bit is set. Not busy. Busy.
Page 803 Chapter 33 Random Number Generator (RNGB) RNG_ESR field descriptions (continued) Field Description RNGB has not failed self test. RNGB has failed self test. Oscillator error. OSCE Indicates the oscillator in the RNG may be broken. This bit is sticky and can only be cleared by a software or hardware reset.
Page 804 Functional Description 33.4 Functional Description The RNGB performs two functional operations, as described in Modes of Operation seed generation and random number generation. Theses operations are performed with cooperation from the major functional blocks in the RNGB described below. 33.4.1 Pseudorandom Number Generator (PRNG) The PRNG implements the NIST-approved PRNG described in the Digital Signature Standard.
Page 805 Chapter 33 Random Number Generator (RNGB) Table 33-8. Reset Summary Affect on External Reset Source Characteristics Internally resets: Signal: Hardware ipg_hard_async_reset_b Active-low, All interface registers — asynchronous, and puts RNGB into minimum 1-cycle the IDLE state Software RNG_CMD[SR] Active-high All interface registers —...
Page 806 Initialization/Application Information Table 33-9. RNG Interrupt Sources RNG_CR Sources Status Bit Field Description Mask Bit Field Seed generation done RNG_SR[SDN] MASKDONE First seed was generated Self test done RNG_SR[STDN] MASKDONE Self test finished Error RNG_SR[ERR] MASKERR Error detected. See RNG_ESR for details. Linear feedback Fault in one of the TRNG's LFSRs RNG_ESR[LSFRE]...
Page 807 Chapter 33 Random Number Generator (RNGB) 33.5.2 Automatic Seeding The intended general operation of the RNGB with automatic seeding enabled is as follows: 1. Reset/initialize. 2. Write to the RNG_CR to setup the RNGB for automatic seeding and the desired functionality.
Page 808 Initialization/Application Information K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 809 Chapter 34 Analog-to-Digital Converter (ADC) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, refer to the Power Management information for the device.
Page 810 Introduction • Input clock selectable from up to four sources • Operation in low power modes for lower noise operation • Asynchronous clock source for lower noise operation with option to output the clock • Selectable hardware conversion trigger with hardware channel select •...
Page 811 Chapter 34 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion SC1n ADHWTSn Trigger Control A D T R G ADHWT (SC2, CFG1, CFG2) C o m p a re tru e Control Registers A D A C K E N Async Clock Gen Interrupt ADACK A D C K...
Page 812 ADC Signal Descriptions Table 34-1. ADC Signal Descriptions (continued) Signal Description DADM[3:0] Differential analog channel inputs AD[23:4] Single-ended analog channel inputs Voltage reference select high REFSH Voltage reference select low REFSL Analog power supply Analog ground 34.2.1 Analog power (V The ADC analog portion uses V as its power connection.
Page 813 Chapter 34 Analog-to-Digital Converter (ADC) In some packages, V is connected in the package to V and V to V . If REFH REFL externally available, the positive reference(s) may be connected to the same potential as or may be driven by an external source to a level between the minimum Ref Voltage High and the V potential (V must never exceed V...
Page 814 Register Definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 34.3.3/ 4003_B00C Configuration register 2 (ADC0_CFG2) 0000_0000h 34.3.4/ 4003_B010 ADC data result register (ADC0_RA) 0000_0000h 34.3.4/ 4003_B014 ADC data result register (ADC0_RB) 0000_0000h 34.3.5/ 4003_B018...
Page 815 Chapter 34 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) ADC minus-side general calibration value register 34.3.21/ 4003_B05C 0000_0200h (ADC0_CLM4) ADC minus-side general calibration value register 34.3.22/ 4003_B060 0000_0100h (ADC0_CLM3) ADC minus-side general calibration value register...
Page 816 Register Definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) ADC plus-side general calibration value register 34.3.13/ 400B_B03C 0000_0200h (ADC1_CLP4) ADC plus-side general calibration value register 34.3.14/ 400B_B040 0000_0100h (ADC1_CLP3) ADC plus-side general calibration value register 34.3.15/ 400B_B044 0000_0080h...
Page 817 Chapter 34 Analog-to-Digital Converter (ADC) Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion. In software trigger mode (ADTRG=0), writes to the SC1A register subsequently initiate a new conversion (if the ADCH bits are equal to a value other than all 1s).
Page 818 Register Definition ADCx_SC1n field descriptions (continued) Field Description Interrupt enable AIEN AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted. Conversion complete interrupt disabled. Conversion complete interrupt enabled. Differential mode enable DIFF DIFF configures the ADC to operate in differential mode.
Page 819 Chapter 34 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 11000 Reserved. 11001 Reserved. 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input.
Page 820 Register Definition ADCx_CFG1 field descriptions (continued) Field Description Normal power configuration. Low power configuration. The power is reduced at the expense of maximum clock speed. 6–5 Clock divide select ADIV ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK. The divide ratio is 1 and the clock rate is input clock.
Page 821 Chapter 34 Analog-to-Digital Converter (ADC) 34.3.3 Configuration register 2 (ADCx_CFG2) CFG2 register selects the special high speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Addresses: ADC0_CFG2 is 4003_B000h base + Ch offset = 4003_B00Ch ADC1_CFG2 is 400B_B000h base + Ch offset = 400B_B00Ch Reset ADLSTS...
Page 822 Register Definition ADCx_CFG2 field descriptions (continued) Field Description ADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCK cycles added to the conversion time) to allow higher speed conversion clocks. Normal conversion sequence selected. High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).
Page 823 Chapter 34 Analog-to-Digital Converter (ADC) Table 34-44. Data result register description (continued) Conversion D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format mode 11-bit differential S Sign extended 2's complement 10-bit single- Unsigned right ended justified...
Page 824 Register Definition The compare value 2 register (CV2) is utilized only when the compare range function is enabled (ACREN=1). Addresses: ADC0_CV1 is 4003_B000h base + 18h offset = 4003_B018h ADC0_CV2 is 4003_B000h base + 1Ch offset = 4003_B01Ch ADC1_CV1 is 400B_B000h base + 18h offset = 400B_B018h ADC1_CV2 is 400B_B000h base + 1Ch offset = 400B_B01Ch Reset ADCx_CVn field descriptions...
Page 825 Chapter 34 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions Field Description 31–8 This read-only field is reserved and always has the value zero. Reserved Conversion active ADACT ADACT indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted.
Page 826 Register Definition ADCx_SC2 field descriptions (continued) Field Description Default voltage reference pin pair (external pins V and V REFH REFL Alternate reference pair (V and V ). This pair may be additional external pins or internal ALTH ALTL sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU.
Page 827 Chapter 34 Analog-to-Digital Converter (ADC) ADCx_SC3 field descriptions (continued) Field Description Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. 5–4 This read-only field is reserved and always has the value zero. Reserved Continuous conversion enable ADCO ADCO enables continuous conversions. One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
Page 828 Register Definition ADCx_OFS field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved 15–0 Offset error correction value 34.3.9 ADC plus-side gain register (ADCx_PG) The plus-side gain register (PG) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode.
Page 829 Chapter 34 Analog-to-Digital Converter (ADC) Addresses: ADC0_MG is 4003_B000h base + 30h offset = 4003_B030h ADC1_MG is 400B_B000h base + 30h offset = 400B_B030h Reset ADCx_MG field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved 15–0 Minus-side gain...
Page 830 Register Definition 34.3.12 ADC plus-side general calibration value register (ADCx_CLPS) For more information, refer to CLPD register description. Addresses: ADC0_CLPS is 4003_B000h base + 38h offset = 4003_B038h ADC1_CLPS is 400B_B000h base + 38h offset = 400B_B038h CLPS Reset ADCx_CLPS field descriptions Field Description 31–6...
Page 831 Chapter 34 Analog-to-Digital Converter (ADC) 34.3.14 ADC plus-side general calibration value register (ADCx_CLP3) For more information, refer to CLPD register description. Addresses: ADC0_CLP3 is 4003_B000h base + 40h offset = 4003_B040h ADC1_CLP3 is 400B_B000h base + 40h offset = 400B_B040h CLP3 Reset ADCx_CLP3 field descriptions...
Page 832 Register Definition 34.3.16 ADC plus-side general calibration value register (ADCx_CLP1) For more information, refer to CLPD register description. Addresses: ADC0_CLP1 is 4003_B000h base + 48h offset = 4003_B048h ADC1_CLP1 is 400B_B000h base + 48h offset = 400B_B048h CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7...
Page 833 Chapter 34 Analog-to-Digital Converter (ADC) 34.3.18 ADC PGA register (ADCx_PGA) Addresses: ADC0_PGA is 4003_B000h base + 50h offset = 4003_B050h ADC1_PGA is 400B_B000h base + 50h offset = 400B_B050h PGAG Reset Reset ADCx_PGA field descriptions Field Description 31–24 This read-only field is reserved and always has the value zero. Reserved PGA enable PGAEN...
Page 834 Register Definition ADCx_PGA field descriptions (continued) Field Description 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 15–0 This read-only field is reserved and always has the value zero. Reserved 34.3.19 ADC minus-side general calibration value register (ADCx_CLMD) CLMx contain calibration information that is generated by the calibration function.
Page 835 Chapter 34 Analog-to-Digital Converter (ADC) 34.3.20 ADC minus-side general calibration value register (ADCx_CLMS) For more information, refer to CLMD register description. Addresses: ADC0_CLMS is 4003_B000h base + 58h offset = 4003_B058h ADC1_CLMS is 400B_B000h base + 58h offset = 400B_B058h CLMS Reset ADCx_CLMS field descriptions...
Page 836 Register Definition 34.3.22 ADC minus-side general calibration value register (ADCx_CLM3) For more information, refer to CLMD register description. Addresses: ADC0_CLM3 is 4003_B000h base + 60h offset = 4003_B060h ADC1_CLM3 is 400B_B000h base + 60h offset = 400B_B060h CLM3 Reset ADCx_CLM3 field descriptions Field Description 31–9...
Page 837 Chapter 34 Analog-to-Digital Converter (ADC) 34.3.24 ADC minus-side general calibration value register (ADCx_CLM1) For more information, refer to CLMD register description. Addresses: ADC0_CLM1 is 4003_B000h base + 68h offset = 4003_B068h ADC1_CLM1 is 400B_B000h base + 68h offset = 400B_B068h CLM1 Reset ADCx_CLM1 field descriptions...
Page 838 Functional description 34.4 Functional description The ADC module is disabled during reset, in low power stop mode (refer to the Power Management information for details), or when the ADCH bits in SC1n are all high. The module is idle when a conversion has completed and another conversion has not been initiated.
Page 839 Chapter 34 Analog-to-Digital Converter (ADC) The PGA has only one voltage reference pair. The positive reference used is chip specific and depends on the MCU configuration. Refer to the Chip Configuration chapter on the PGA Voltage Reference specific to this MCU. The ground reference is the analog ground for the PGA.
Page 840 Functional description 34.4.3 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (V and V ) used for conversions. Each pair contains a REFSH REFSL positive reference that must be between the minimum Ref Voltage High and V , and a ground reference that must be at the same potential as V .
Page 841 Chapter 34 Analog-to-Digital Converter (ADC) When the conversion is completed, the result is placed in the data registers associated with the ADHWTSn received (ADHWTSA active selects RA register; ADHWTSn active selects Rn register). The conversion complete flag associated with the ADHWTSn received (the COCO bit in SC1n register) is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled (AIEN=1).
Page 842 Functional description If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after SC1A register is written and continue until aborted. In hardware triggered operation (ADTRG=1 and one ADHWTSn event has occurred), continuous conversions begin after a hardware trigger event and continue until aborted.
Page 843 Chapter 34 Analog-to-Digital Converter (ADC) • The MCU is reset or enters Low Power Stop modes. • The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion.
Page 844 Functional description ADC Configuration Sample time (ADCK cycles) The total conversion time depends upon: the sample time (as determined by ADLSMP and ADLSTS bits), the MCU bus frequency, the conversion mode (as determined by MODE and SC1n[DIFF] bits), the high speed configuration (ADHSC bit), and the frequency of the conversion clock (f ADCK The ADHSC bit is used to configure a higher clock input frequency.
Page 845 Chapter 34 Analog-to-Digital Converter (ADC) Table 34-108. Average number factor (AverageNum) AVGE AVGS[1:0] Average number factor (AverageNum) Table 34-109. Base Conversion Time (BCT) Mode Base conversion time (BCT) 8b s.e. 17 ADCK cycles 9b diff 27 ADCK cycles 10b s.e. 20 ADCK cycles 11b diff 30 ADCK cycles...
Page 846 Functional description 34.4.5.6 Conversion time examples The following examples use Figure 34-95 and the information provided in Table 34-107 through Table 34-111. 34.4.5.6.1 Typical conversion time configuration A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, long sample time disabled and high speed conversion disabled.
Page 847 Chapter 34 Analog-to-Digital Converter (ADC) Table 34-113. Typical conversion time (continued) Variable Time HSCAdder The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting conversion time is 57.625 µs (AverageNum).
Page 848 Functional description After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions has been completed. When hardware averaging is selected, the completion of a single conversion will not set the COCO bit.
Page 849 Chapter 34 Analog-to-Digital Converter (ADC) With the ADC range enable bit set, ACREN =1, and if compare value register 1 (CV1 value) is less than or equal to the compare value register 2 (CV2 value), then setting ACFGT will select a trigger-if-inside-compare-range inclusive-of-endpoints function. Clearing ACFGT will select a trigger-if-outside-compare-range, not-inclusive-of- endpoints function.
Page 850 Functional description for the different configurations. For best calibration results, it is recommended to set hardware averaging to maximum (AVGE=1, AVGS=11 for average of 32), ADC clock frequency f less than or equal to 4 MHz, V , and to calibrate at nominal ADCK REFH voltage and temperature.
Page 851 Chapter 34 Analog-to-Digital Converter (ADC) stored in flash memory after an initial calibration and recovered prior to the first ADC conversion. This method should reduce the calibration latency to 20 register store operations on all subsequent power, reset, or Low Power Stop mode recoveries. 34.4.8 User defined offset function The ADC offset correction register (OFS) contains the user selected or calibration generated offset error correction value.
Page 852 Functional description format and the effect will be an addition. An offset correction that results in an out-of- range value will be forced to the minimum or maximum value (the minimum value for single-ended conversions is 0x0000; for a differential conversion it is 0x8000). To preserve accuracy, the calibrated offset value initially stored in the OFS register must be added to the user defined offset.
Page 853 Chapter 34 Analog-to-Digital Converter (ADC) 34.4.10 MCU wait mode operation Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters Wait mode, it continues until completion. Conversions can be initiated while the MCU is in Wait mode by means of the hardware trigger or if continuous conversions are enabled.
Page 854 Initialization information 34.4.11.2 Normal Stop mode with ADACK enabled If ADACK is selected as the conversion clock, the ADC continues operation during Normal Stop mode. Refer to the Chip Configuration chapter for configuration information for this MCU. If a conversion is in progress when the MCU enters Normal Stop mode, it continues until completion.
Page 855 Chapter 34 Analog-to-Digital Converter (ADC) Note Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 34.5.1 ADC module initialization example This section provides details about the ADC module initialization. 34.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed.
Page 856 Initialization information CFG1 = 0x98 (%10011000) Bit 7 ADLPC Configures for low power (lowers maximum clock speed. Bit 6:5 ADIV Sets the ADCK to the input clock ÷ 1. Bit 4 ADLSMP Configures for long sample time. Bit 3:2 MODE Selects the single-ended 10-bit conversion, differential 11- bit conversion.
Page 857 Chapter 34 Analog-to-Digital Converter (ADC) Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check SC1n[COCO]=1? Read Rn to clear SC1n[COCO] bit Continue Figure 34-97. Initialization Flowchart for Example 34.6 Application information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC.
Page 858 Application information supply pins. In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both V and V must be connected to the same voltage potential as their corresponding MCU digital supply (V...
Page 859 Chapter 34 Analog-to-Digital Converter (ADC) frequency characteristics. This capacitor is connected between V and V REFH REFL must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors.
Page 860 Application information SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2 LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP and changing the ADLSTS bits (to increase the sample window) or decreasing ADCK frequency to increase sample time.
Page 861 Chapter 34 Analog-to-Digital Converter (ADC) • For software triggered conversions, immediately follow the write to the SC1 register with a wait instruction or stop instruction. • For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces V noise but increases effective conversion time due to stop recovery.
Page 862 Application information For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB. 34.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers should be aware of them because they affect overall accuracy.
Page 863 Chapter 34 Analog-to-Digital Converter (ADC) This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage.
Page 864 Application information K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 865 Chapter 35 Comparator (CMP) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Comparator module (CMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation).
Page 866 6-bit DAC Key Features • Selectable interrupt on rising edge, falling edge, or both rising or falling edges of comparator output • Selectable inversion on comparator output • Comparator output may be: • Sampled • Windowed (ideal for certain PWM zero-crossing-detection applications) •...
Page 867 Chapter 35 Comparator (CMP) 35.4 ANMUX Key Features • Two 8 to 1 channel mux • Operates the entire supply range 35.5 CMP, DAC, and ANMUX Diagram The following figure shows the block diagram for the High Speed Comparator, Digital to Analog Converter, and Analog MUX modules.
Page 868 CMP Block Diagram VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample Input Reference Input 5 Reference Input 6 Window ANMUX and Filter control CMPO MSEL[2:0] Figure 35-1. CMP, DAC and ANMUX Blocks Diagram 35.6 CMP Block Diagram The following figure shows the block diagram for the Comparator module.
Page 869 Chapter 35 Comparator (CMP) INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSCTRL[1:0] Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided Prescaler FILT_PER CGMUX clock Figure 35-2. Comparator Module Block Diagram In the CMP block diagram: •...
Page 870 Memory Map/Register Definitions • If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on COUT due to the fact that COUT (which is crossing clock domain boundaries) must be resynchronized to the bus clock. •...
Page 871 Chapter 35 Comparator (CMP) CMP memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 35.7.3/ 4007_3012 CMP Filter Period Register (CMP2_FPR) 35.7.4/ 4007_3013 CMP Status and Control Register (CMP2_SCR) 35.7.5/ 4007_3014 DAC Control Register (CMP2_DACCR) 35.7.6/ 4007_3015 MUX Control Register (CMP2_MUXCR)
Page 872 Memory Map/Register Definitions CMPx_CR0 field descriptions (continued) Field Description This read-only field is reserved and always has the value zero. Reserved 1–0 Comparator hard block hysteresis control HYSTCTR Defines the programmable hysteresis level. The hysteresis values associated with each level is device- specific.
Page 873 Chapter 35 Comparator (CMP) CMPx_CR1 field descriptions (continued) Field Description Refer to the device data sheet's CMP electrical specifications table for details on the impact of the modes below. Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
Page 874 Memory Map/Register Definitions CMPx_FPR field descriptions Field Description 7–0 Filter Sample Period FILT_PER When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the Functional Description.
Page 875 Chapter 35 Comparator (CMP) CMPx_SCR field descriptions (continued) Field Description Interrupt disabled. Interrupt enabled. Comparator Interrupt Enable Falling The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted when the CFF bit is set. Interrupt disabled.
Page 876 Memory Map/Register Definitions CMPx_DACCR field descriptions Field Description DAC Enable DACEN This bit is used to enable the DAC. When the DAC is disabled, it is powered down to conserve power. DAC is disabled. DAC is enabled. Supply Voltage Reference Source Select VRSEL is selected as resistor ladder network supply reference Vin.
Page 877 Chapter 35 Comparator (CMP) CMPx_MUXCR field descriptions (continued) Field Description 5–3 Plus Input MUX Control PSEL Determines which input is selected for the plus input of the comparator. For INx inputs, refer to CMP, DAC and ANMUX Blocks Diagram. NOTE: When an inappropriate operation selects the same input for both MUXes, the comparator automatically shuts down to prevent itself from becoming a noise generator.
Page 878 CMP Functional Description 35.8.1 CMP Functional Modes There are three main sub-blocks to the comparator module: the comparator itself, the window function and the filter function. The filter, CR0[FILTER_CNT] can be clocked from an internally or external clock source. Additionally, the filter is programmable with respect to how many samples must agree before a change on the output is registered.
Page 879 Chapter 35 Comparator (CMP) Table 35-29. Comparator Sample/Filter Controls (continued) CR0[FILTER_C Mode # CR1[EN] CR1[WE] CR1[SE] FPR[FILT_PER] Operation 0x01 0x01 - 0xFF Windowed/Resampled mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT.
Page 880 CMP Functional Description 35.8.1.2 Continuous Mode (#s 2A & 2B) INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSTCTR[1:0] Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided Prescaler FILT_PER CGMUX...
Page 881 Chapter 35 Comparator (CMP) 35.8.1.3 Sampled, Non-Filtered Mode (#s 3A & 3B) INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSTCTR[1:0] 0x01 Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided Prescaler...
Page 882 CMP Functional Description INTERNAL BUS FILT_PER EN,PMODE,HYSTCTR[1:0] FILTER_CNT COUT IER/F CFR/F 0x01 Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided bus clock Prescaler FILT_PER CGMUX SE=0 Figure 35-29.
Page 883 Chapter 35 Comparator (CMP) INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0] > 0x01 Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided Prescaler FILT_PER CGMUX clock SE=1...
Page 884 CMP Functional Description INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSTCTR[1:0 > 0x01 Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided Prescaler FILT_PER CGMUX clock SE=0 Figure 35-31.
Page 885 Chapter 35 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 35-32. Windowed Mode Operation INTERNAL BUS FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSCTR[1:0] 0x01 Window Interrupt Polarity Filter Control Select Control Block CMPO COUT (TO OTHER SOC FUNCTIONS)) WINDOW/SAMPLE bus clock Clock...
Page 886 CMP Functional Description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 35.8.1.6 Windowed/Resampled Mode (# 6) The following figure uses the same input stimulus shown in Figure 35-32, and adds resampling of COUTA to generate COUT.
Page 887 Chapter 35 Comparator (CMP) 35.8.1.7 Windowed/Filtered Mode (#7) This is the most complex mode of operation for the comparator block, as it utilizes both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] X FPR[FILT_PER]) + 1) X bus clock for the filter function.
Page 888 CMP Functional Description 35.8.2.2 Stop Mode Operation Subject to platform-specific clock restrictions, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 889 Chapter 35 Comparator (CMP) 35.8.4 Low Pass Filter The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT. Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system.
Page 890 CMP Functional Description If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when CR0[FILTER_CNT] consecutive samples all agree that the output value has changed. 35.8.4.2 Latency Issues The FPR[FILT_PER] value (or SAMPLE period) should be set such that the sampling period is just larger than the period of the expected noise.
Page 891 Chapter 35 Comparator (CMP) Table 35-30. Comparator Sample/Filter Maximum Latencies (continued) CR1[ CR1[ CR1[ CR0[FILTER FPR[FILT_P Mode # Operation Maximum Latency _CNT] > 0x01 0x01 - 0xFF Windowed / Filtered mode + (CR0[FILTER_CNT] x FPR[FILT_PER] x T 1. T represents the intrinsic delay of the analog component plus the polarity select logic. T is the clock period of the SAMPLE external sample clock.
Page 892 DAC Functional Description DACEN VOSEL[5:0] VRSEL DACO Figure 35-36. 6-bit DAC Block Diagram 35.12 DAC Functional Description This section provides DAC functional description. 35.12.1 Voltage Reference Source Select • V should be used to connect to the primary voltage source as supply reference of 64 tap resistor ladder •...
Page 893 Chapter 35 Comparator (CMP) 35.15 DAC Interrupts This module has no interrupts. K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 894 DAC Interrupts K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 895 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 12-bit digital-to-analog converter (DAC) is a low power general purpose DAC. The output of this DAC can be placed on an external pin or set as one of the inputs to the analog comparator, Op-Amps, ADC, or other peripherals.
Page 896 Memory Map/Register Definition DACREF_2 DACREF_1 DACRFS DACRFS AMP Buffer DACEN LPEN Vout DACDAT[11:0] Hardware Trigger DACBFWMF & DACBWIEN DACSWTRG DACBFWM DACBFRPTF dac_interrupt DATA & DACBFEN BUFFER DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 36-1. DAC Block Diagram 36.4 Memory Map/Register Definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions.
Page 897 Chapter 36 12-bit Digital-to-Analog Converter (DAC) DAC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.4.1/ 400C_C000 DAC Data Low Register (DAC0_DAT0L) 36.4.2/ 400C_C001 DAC Data High Register (DAC0_DAT0H) 36.4.1/ 400C_C002 DAC Data Low Register (DAC0_DAT1L) 36.4.2/ 400C_C003 DAC Data High Register (DAC0_DAT1H)
Page 898 Memory Map/Register Definition DAC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.4.1/ 400C_C014 DAC Data Low Register (DAC0_DAT10L) 36.4.2/ 400C_C015 DAC Data High Register (DAC0_DAT10H) 36.4.1/ 400C_C016 DAC Data Low Register (DAC0_DAT11L) 36.4.2/ 400C_C017 DAC Data High Register (DAC0_DAT11H)
Page 899 Chapter 36 12-bit Digital-to-Analog Converter (DAC) DAC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.4.1/ 400C_D004 DAC Data Low Register (DAC1_DAT2L) 36.4.2/ 400C_D005 DAC Data High Register (DAC1_DAT2H) 36.4.1/ 400C_D006 DAC Data Low Register (DAC1_DAT3L) 36.4.2/ 400C_D007 DAC Data High Register (DAC1_DAT3H)
Page 900 Memory Map/Register Definition DAC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.4.1/ 400C_D018 DAC Data Low Register (DAC1_DAT12L) 36.4.2/ 400C_D019 DAC Data High Register (DAC1_DAT12H) 36.4.1/ 400C_D01A DAC Data Low Register (DAC1_DAT13L) 36.4.2/ 400C_D01B DAC Data High Register (DAC1_DAT13H) 36.4.1/...
Page 901 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.4.2 DAC Data High Register (DACx_DATH) Addresses: 400C_C000h base + 1h offset + (2d × n), where n = 0d to 15d Read DATA[11:8] Write Reset DACx_DATnH field descriptions Field Description 7–4 This read-only field is reserved and always has the value zero. Reserved 3–0 When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following...
Page 902 Memory Map/Register Definition DACx_SR field descriptions (continued) Field Description The DAC buffer read pointer is not zero. The DAC buffer read pointer is zero. DAC buffer read pointer bottom position flag DACBFRPBF The DAC buffer read pointer is not equal to the DACBFUP. The DAC buffer read pointer is equal to the DACBFUP.
Page 903 Chapter 36 12-bit Digital-to-Analog Converter (DAC) DACx_C0 field descriptions (continued) Field Description high power mode. low power mode. DAC buffer watermark interrupt enable DACBWIEN The DAC buffer watermark interrupt is disabled. The DAC buffer watermark interrupt is enabled. DAC buffer read pointer top flag interrupt enable DACBTIEN The DAC buffer read pointer top flag interrupt is disabled.
Page 904 Functional Description DACx_C1 field descriptions (continued) Field Description 2–1 DAC buffer work mode select DACBFMD Normal Mode Swing Mode One-Time Scan Mode Reserved DAC buffer enable DACBFEN Buffer read pointer disabled. The converted data is always the first word of the buffer. Buffer read pointer enabled.
Page 905 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.5.1 DAC Data Buffer Operation When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage. When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage.
Page 906 Functional Description 36.5.1.4 Buffer One-time Scan Mode The read pointer increases by one every time when the trigger occurs. When it reaches the upper limit, it stops at there. If read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop at there again.
Page 907 Chapter 36 12-bit Digital-to-Analog Converter (DAC) NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 908 Functional Description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 909 Chapter 37 Operational Amplifier (OPAMP) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The General Purpose Operational Amplifier (OPAMP) block is a CMOS single supply, low-input offset voltage, low-input offset, and bias current amplifier that is designed for low-voltage, low-power operation over an input voltage range of 0 to supply.
Page 910 Introduction 37.1.2 Block Diagram This diagram illustrates the op-amp module. NOTE The positive and negative inputs are specific to the device using this module. See the device's Chip Configuration details for the connections used for these inputs. AMPNSEL Inverting/ AMPRF Negative Input 0 non-inverting Negative Input 1...
Page 911 Chapter 37 Operational Amplifier (OPAMP) 37.1.4 Operating modes The following table shows the valid C0[MODE] and C1[AMPRI, AMPRF] settings. Using a reserved mode results in unpredictable behavior. Table 37-1. Operating modes C0[MODE] C1[AMPRI] C1[AMPRF] Gain Function — Buffer mode — General amplifier mode —...
Page 912 Introduction Table 37-1. Operating modes (continued) C0[MODE] C1[AMPRI] C1[AMPRF] Gain Function — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved Inverting PGA mode Inverting PGA mode — Reserved Non-inverting PGA mode Non-inverting PGA mode Non-inverting PGA mode Non-inverting PGA mode Non-inverting PGA mode Non-inverting PGA mode...
Page 913 Chapter 37 Operational Amplifier (OPAMP) Table 37-1. Operating modes (continued) C0[MODE] C1[AMPRI] C1[AMPRF] Gain Function — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved Non-inverting PGA mode Non-inverting PGA mode 37.2 Signal Description Table 37-2. Signal Properties Name Description Amplifier positive input terminal...
Page 914 Memory Map and Registers 37.3 Memory Map and Registers This section provides a detailed description of all memory and registers. OPAMP memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.3.1/ 400F_5000 Control Register 0 (OPAMP0_C0) 37.3.2/ 400F_5001 Control Register 1 (OPAMP0_C1)
Page 915 Chapter 37 Operational Amplifier (OPAMP) OPAMPx_C0 field descriptions (continued) Field Description High-speed mode selected. In this mode, OPAMP has faster slew rate and unity gain bandwidth performance with higher current consumption. Low-power mode selected. In this mode, OPAMP has lower current consumption with slower slew rate and unity gain bandwidth performance.
Page 916 Memory Map and Registers 37.3.3 Control Register 2 (OPAMPx_C2) Addresses: OPAMP0_C2 is 400F_5000h base + 2h offset = 400F_5002h OPAMP1_C2 is 400F_5800h base + 2h offset = 400F_5802h Read AMPPSEL AMPNSEL Write Reset OPAMPx_C2 field descriptions Field Description This read-only field is reserved and always has the value zero. Reserved 6–4 Amplifier Positive Input Terminal Selector...
Page 917 Chapter 37 Operational Amplifier (OPAMP) 37.4 Functional Description This section provides a complete functional description of the OPAMP block, detailing the operation of the design from the end-user perspective. 37.4.1 Operational Amplifier Configuration The following is a block diagram of the OPAMP module in general purpose mode. AMPNSEL Inverting/ AMPRF...
Page 918 Functional Description AMPNSEL Inverting/ AMPRF Negative Input 0 non-inverting Negative Input 1 AMPRI control Negative Input 2 Negative Input 3 Negative Input 4 Negative Input 5 Programmable Negative Input 6 resistor network Negative Input 7 Mode select MODE Positive Input 0 Positive Input 1 Positive Input 2 –...
Page 919 Chapter 37 Operational Amplifier (OPAMP) AMPNSEL Inverting/ AMPRF Negative Input 0 non-inverting Negative Input 1 AMPRI control Negative Input 2 Negative Input 3 Negative Input 4 Negative Input 5 Programmable Negative Input 6 resistor network Negative Input 7 Mode select MODE Positive Input 0 Positive Input 1...
Page 920 Functional Description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 921 Chapter 38 Transimpedance Amplifier (TRIAMP) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The TRIAMP block is a CMOS single supply, low input offset voltage, low input offset and bias current amplifier that is designed for low-voltage, low-power operation. The TRIAMP also has control settings that can be software-configured depending on application requirements.
Page 922 Introduction 38.1.3 Block Diagram This diagram illustrates the TRIAMP module. lpen_lv inn_3v – out_3v inp_3v en_lv Figure 38-1. TRIAMP Block Diagram 38.1.4 Signal Description The TRIAMP module has the following external pins. Table 38-1. Signal Properties Name Function Direction inp_3v Amplifier positive input terminal inn_3v Amplifier negative input terminal...
Page 923 Chapter 38 Transimpedance Amplifier (TRIAMP) 38.2 Memory Map/Register Definition TRIAMP memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 38.2.1/ 400F_8000 Control Register 0 (TRIAMP0_C0) 38.2.1/ 400F_8800 Control Register 0 (TRIAMP1_C0) 38.2.1 Control Register 0 (TRIAMPx_C0) Addresses: TRIAMP0_C0 is 400F_8000h base + 0h offset = 400F_8000h TRIAMP1_C0 is 400F_8800h base + 0h offset = 400F_8800h Read...
Page 924 Functional Description 38.3 Functional Description This section provides a complete functional description of the TRIAMP block, detailing the operation of the design from the end-user perspective. 38.3.1 Trans-Impedance Amplifier Configuration 38.3.2 Photodiode Zero-Biased Operation The following figure shows a typical application (supply is 3 V) diagram of the TRIAMP module.
Page 925 Chapter 38 Transimpedance Amplifier (TRIAMP) out_3v I photo inn_3v λ photodiode OUT=V photo inp_3v 1.6 > V dac > 0 off_chip Figure 38-6. Reverse-Biased Application Diagram Table 38-8. TRIAMP Module OUT = I × R (Ω) photo photo 1 nA 0.201 V 10 nA 0.210 V...
Page 926 Functional Description K53 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc.
Page 927 Chapter 39 Voltage Reference (VREFV1) 39.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The VREFV1 Voltage Reference is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREFV1 can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
Page 928 Introduction 1.75 V Regulator SC[VREFST] 1.75 V 6 BITS DEDICATED BANDGAP OUTPUT PIN VDDA SC[VREFEN] VREF_OUT 2 BITS SC[MODE_LV] 100 nF REGULATION BUFFER VSSA Figure 39-1. Voltage reference block diagram 39.1.1 Overview The Voltage Reference provides a buffered reference voltage with high output current for use as an external reference.
Page 929 Chapter 39 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Tight-regulation buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT • Load regulation in tight-regulation mode 39.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes.
Page 930 Memory Map and Register Definition VREF memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 39.2.1/ 4007_4000 VREF Trim Register (VREF_TRM) Undefined 39.2.2/ 4007_4001 VREF Status and Control Register (VREF_SC) 39.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference.
Page 931 Chapter 39 Voltage Reference (VREFV1) 39.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the VREF mode to be used. Address: VREF_SC is 4007_4000h base + 1h offset = 4007_4001h Read VREFST VREFEN...
Page 932 Functional Description VREF_SC field descriptions (continued) Field Description Tight-regulation buffer enabled Reserved 39.3 Functional Description The Voltage Reference is a bandgap buffer system. Unity gain amplifiers are used. The VREF_OUT signal is available as an internal reference when it is enabled. A 100 nF capacitor must be connected between VREF_OUT and VSSA.
Page 933 Chapter 39 Voltage Reference (VREFV1) 39.3.2.1 SC[MODE_LV]=00 The internal bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time for startup and stabilization. SC[VREFST] can be monitored to determine if the stabilization and startup is complete.
Page 934 Initialization/Application Information When the Voltage Reference is already enabled and stabilized, changing SC[MODE_LV] will not clear SC[VREFST] but there will be some startup time before the output voltage at the VREF_OUT pin has settled. This is the buffer start up delay (Tstup) and the value is specified in the appropriate device data sheet.
Page 935 Chapter 40 Programmable Delay Block (PDB) 40.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The programmable delay block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved.
Page 936 Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support •...
Page 937 Chapter 40 Programmable Delay Block (PDB) • Y — Total number of Pulse-Out's. • y — Pulse-Out number, valid value is 0 to Y-1. NOTE The number of module output triggers to core are chip-specific. For module to core output triggers implementation, refer to the Chip Configuration information.
Page 938 Introduction Ack 0 PDBCHnDLY0 Pre-trigger 0 BB[0], TOS[0] EN[0] Ch n pre-trigger 0 Ack m PDBCHnDLYm Pre-trigger m BB[m], TOS[m] EN[m] Ch n pre-trigger m Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD Control DACINTx Logic DAC interval trigger x PDBCNT DAC Interval Counter x...
Page 939 Chapter 40 Programmable Delay Block (PDB) 40.1.6 Modes of Operation PDB ADC trigger operates in the following modes. Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in back- to-back operation of Bypass mode. Debug: Counter is paused when processor is in debug mode, the counter for dac trigger also paused in Debug mode.
Page 940 Memory Map and Register Definition PDB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 40.3.1/ 4003_6000 Status and Control Register (PDB0_SC) 0000_0000h 40.3.2/ 4003_6004 Modulus Register (PDB0_MOD) 0000_FFFFh 40.3.3/ 4003_6008 Counter Register (PDB0_CNT) 0000_0000h 40.3.4/ 4003_600C...
Page 941 Chapter 40 Programmable Delay Block (PDB) 40.3.1 Status and Control Register (PDBx_SC) Addresses: PDB0_SC is 4003_6000h base + 0h offset = 4003_6000h LDMOD Reset PRESCALER TRGSEL MULT Reset PDBx_SC field descriptions Field Description 31–20 This read-only field is reserved and always has the value zero. Reserved 19–18 Load Mode Select...
Page 942 Memory Map and Register Definition PDBx_SC field descriptions (continued) Field Description DMA Enable DMAEN When DMA is enabled, the PDBIF flag generates a DMA request instead of an interrupt. DMA disabled DMA enabled 14–12 Prescaler Divider Select PRESCALER Counting uses the peripheral clock divided by multiplication factor selected by MULT. Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
Page 943 Chapter 40 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description This bit is set when the counter value is equal to the IDLY register. Writing zero clears this bit. PDB Interrupt Enable. PDBIE This bit enables the PDB interrupt. When this bit is set and DMAEN is cleared, PDBIF generates a PDB interrupt.
Page 944 Memory Map and Register Definition PDBx_MOD field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved 15–0 PDB Modulus. These bits specify the period of the counter. When the counter reaches this value, it will be reset back to zero.
Page 945 Chapter 40 Programmable Delay Block (PDB) PDBx_IDLY field descriptions (continued) Field Description These bits specify the delay value to schedule the PDB interrupt. It can be used to schedule an independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is equal to the IDLY.
Page 946 Memory Map and Register Definition PDBx_CHnC1 field descriptions (continued) Field Description These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this MCU. PDB channel's corresponding pre-trigger disabled. PDB channel's corresponding pre-trigger enabled. 40.3.6 Channel n Status Register (PDBx_CHS) Addresses: PDB0_CH0S is 4003_6000h base + 14h offset = 4003_6014h PDB0_CH1S is 4003_6000h base + 3Ch offset = 4003_603Ch Reset...
Page 947 Chapter 40 Programmable Delay Block (PDB) 40.3.7 Channel n Delay 0 Register (PDBx_CHDLY0) Addresses: PDB0_CH0DLY0 is 4003_6000h base + 18h offset = 4003_6018h PDB0_CH1DLY0 is 4003_6000h base + 40h offset = 4003_6040h Reset PDBx_CHnDLY0 field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved 15–0 PDB Channel Delay...
Page 948 Memory Map and Register Definition 40.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn) Addresses: PDB0_DACINTC0 is 4003_6000h base + 150h offset = 4003_6150h PDB0_DACINTC1 is 4003_6000h base + 158h offset = 4003_6158h Reset PDBx_DACINTCn field descriptions Field Description 31–2 This read-only field is reserved and always has the value zero. Reserved DAC External Trigger Input Enable This bit enables the external trigger for DAC interval counter.
Page 949 Chapter 40 Programmable Delay Block (PDB) PDBx_DACINTn field descriptions (continued) Field Description 15–0 DAC Interval These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal register that is effective for the current PDB cycle.
Page 950 Functional Description PDBx_POnDLY field descriptions (continued) Field Description These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is equal to the DLY1. Reading these bits returns the value of internal register that is effective for the current PDB cycle.
Page 951 Chapter 40 Programmable Delay Block (PDB) Trigger input event Ch n pre-trigger 0 Ch n pre-trigger 1 .... Ch n pre-trigger M Ch n trigger Figure 40-52. Pre-trigger and Trigger Outputs The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is cleared.
Page 952 Functional Description 40.4.2 PDB Trigger Input Source Selection The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are connected to on-chip or off-chip event sources. The PDB can be triggered by software through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or software trigger.
Page 953 Chapter 40 Programmable Delay Block (PDB) MOD, IDLY CHnDLY1 CHnDLY0 DACINTx x3 DACINTx x2 DACINTx counter Trigger input event .... DAC internal trigger x Ch n pre-trigger 0 Ch n pre-trigger 1 Ch n trigger PDB interrupt Figure 40-53.
Page 954 Functional Description • PDB Modulus Register (MOD) • PDB Interrupt Delay Register (IDLY) • PDB Channel n Delay m Register (CHnDLYm) • DAC Interval x Register (DACINTx) • PDB Pulse-Out y Delay Register (POyDLY) The internal registers of them are buffered and any values written to them are written first to their buffers.
Page 955 Chapter 40 Programmable Delay Block (PDB) CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 40-55. Registers Update with SC[LDMOD] = x1 40.4.6 Interrupts PDB can generate two interrupts, PDB interrupt and PDB sequence error interrupt. The following table summarizes the interrupts.
Page 956 Application Information values of total peripheral clocks that can be detected are even values; if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod(4) and so forth. If the applications need a really long delay value and use 128, then the resolution would be limited to 128 peripheral clock cycles.
Page 957 Chapter 41 FlexTimer (FTM) 41.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexTimer Module (FTM) is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications.
Page 958 Introduction FlexTimer input triggers can be from comparators, ADC or other sub modules to initiate timer functions automatically. These triggers can be linked in a variety of ways during integration of the sub modules so please note carefully the options available for used FlexTimer configuration.
Page 959 Chapter 41 FlexTimer (FTM) • Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of PWM signal) • The FTM channels can operate as pairs with equal outputs, pairs with complementary outputs, or independent channels (with independent outputs) •...
Page 960 Introduction 41.1.4 Block Diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down.
Page 961 Chapter 41 FlexTimer (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock prescaler external clock synchronizer ( 1, 2, 4, 8, 16, 32, 64 or 128) phase A Quadrature decoder phase B QUADEN CPWMS CAPTEST INITTRIGEN initialization...
Page 962 FTM Signal Descriptions 41.2 FTM Signal Descriptions Table 41-1 shows the user-accessible signals for the FTM. Table 41-1. FTM Signal Descriptions Signal Description EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 FAULTj Fault input (j), where j can be 3-0 Quadrature decoder phase A input.
Page 963 Chapter 41 FlexTimer (FTM) defined for each pair of channels. Since there are several FAULTj inputs, maximum of 4 for the FTM module, each one of these inputs is activated by the FAULTjEN bit in the FLTCTRL register. 41.2.4 PHA — FTM Quadrature Decoder Phase A Input The quadrature decoder phase A input is used as the quadrature decoder mode is selected.
Page 964 Memory Map and Register Definition 41.3.2 Register Descriptions This section consists of register descriptions in address order. Accesses to reserved addresses result in transfer errors. Registers for absent channels are considered reserved. FTM memory map Absolute Width Section/ address Register name Access Reset value (in bits)
Page 965 Chapter 41 FlexTimer (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.7/ 4003_8040 Channel (n) Value (FTM0_C6V) 0000_0000h 41.3.6/ 4003_8044 Channel (n) Status and Control (FTM0_C7SC) 0000_0000h 41.3.7/ 4003_8048 Channel (n) Value (FTM0_C7V) 0000_0000h 41.3.8/ 4003_804C...
Page 966 Memory Map and Register Definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.25/ 4003_8090 FTM Inverting Control (FTM0_INVCTRL) 0000_0000h 1010 41.3.26/ 4003_8094 FTM Software Output Control (FTM0_SWOCTRL) 0000_0000h 1011 41.3.27/ 4003_8098 FTM PWM Load (FTM0_PWMLOAD) 0000_0000h...
Page 967 Chapter 41 FlexTimer (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.6/ 4003_9044 Channel (n) Status and Control (FTM1_C7SC) 0000_0000h 41.3.7/ 4003_9048 Channel (n) Value (FTM1_C7V) 0000_0000h 41.3.8/ 4003_904C Counter Initial Value (FTM1_CNTIN) 0000_0000h 41.3.9/ 4003_9050...
Page 968 Memory Map and Register Definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.26/ 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 0000_0000h 1011 41.3.27/ 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 0000_0000h 1013 41.3.3/ 400B_8000 Status and Control (FTM2_SC) 0000_0000h...
Page 969 Chapter 41 FlexTimer (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.7/ 400B_8048 Channel (n) Value (FTM2_C7V) 0000_0000h 41.3.8/ 400B_804C Counter Initial Value (FTM2_CNTIN) 0000_0000h 41.3.9/ 400B_8050 Capture and Compare Status (FTM2_STATUS) 0000_0000h 41.3.10/ 400B_8054...
Page 970 Memory Map and Register Definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 41.3.27/ 400B_8098 FTM PWM Load (FTM2_PWMLOAD) 0000_0000h 1013 41.3.3 Status and Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor.
Page 971 Chapter 41 FlexTimer (FTM) FTMx_SC field descriptions (continued) Field Description Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-aligned PWM Select CPWMS Selects CPWM mode. This mode configures the FTM to operate in up-down counting mode. This field is write protected.
Page 972 Memory Map and Register Definition Addresses: FTM0_CNT is 4003_8000h base + 4h offset = 4003_8004h FTM1_CNT is 4003_9000h base + 4h offset = 4003_9004h FTM2_CNT is 400B_8000h base + 4h offset = 400B_8004h COUNT Reset FTMx_CNT field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero.
Page 973 Chapter 41 FlexTimer (FTM) FTMx_MOD field descriptions (continued) Field Description 15–0 Modulo value 41.3.6 Channel (n) Status and Control (FTMx_CSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 41-67. Mode, Edge, and Level Selection DECAPEN COMBINE CPWMS...
Page 974 Memory Map and Register Definition Table 41-67. Mode, Edge, and Level Selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration Input capture Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Output compare Toggle Output on match Clear Output on...
Page 975 Chapter 41 FlexTimer (FTM) Table 41-68. Dual Edge Capture Mode — Edge Polarity Selection ELSnB ELSnA Channel Port Enable Detected Edges Disabled No edge Enabled Rising edge Enabled Falling edge Enabled Rising and falling edges Addresses: FTM0_C0SC is 4003_8000h base + Ch offset = 4003_800Ch Reset Reset FTMx_CnSC field descriptions...
Page 976 Memory Map and Register Definition FTMx_CnSC field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. Channel Mode Select Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 41-7.
Page 977 Chapter 41 FlexTimer (FTM) FTMx_CnV field descriptions Field Description 31–16 This read-only field is reserved and always has the value zero. Reserved 15–0 Channel Value Captured FTM counter value of the input modes or the match value for the output modes 41.3.8 Counter Initial Value (FTMx_CNTIN) The Counter Initial Value register contains the initial value for the FTM counter.
Page 978 Memory Map and Register Definition Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel.
Page 979 Chapter 41 FlexTimer (FTM) FTMx_STATUS field descriptions (continued) Field Description No channel event has occurred. A channel event has occurred. Channel 4 Flag CH4F See the register description. No channel event has occurred. A channel event has occurred. Channel 3 Flag CH3F See the register description.
Page 980 Memory Map and Register Definition 41.3.10 Features Mode Selection (FTMx_MODE) This register contains the control bits used to configure the fault interrupt and fault control, capture test mode, PWM synchronization, write protection, channel output initialization, and enable the enhanced features of the FTM. These controls relate to all channels within this module.
Page 981 Chapter 41 FlexTimer (FTM) FTMx_MODE field descriptions (continued) Field Description Capture Test Mode Enable CAPTEST Enables the capture test mode. This field is write protected. It can be written only when MODE[WPDIS] = 1. Capture test mode is disabled. Capture test mode is enabled. PWM Synchronization Mode PWMSYNC Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization...
Page 982 Memory Map and Register Definition NOTE The software trigger (SWSYNC bit) and hardware triggers (TRIG0, TRIG1, and TRIG2 bits) have a potential conflict if used together when SYNCMODE = 0. It is recommended using only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen.
Page 983 Chapter 41 FlexTimer (FTM) FTMx_SYNC field descriptions (continued) Field Description Software trigger is not selected. Software trigger is selected. PWM Synchronization Hardware Trigger 2 TRIG2 Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal.
Page 984 Memory Map and Register Definition FTMx_SYNC field descriptions (continued) Field Description The minimum loading point is disabled. The minimum loading point is enabled. 41.3.12 Initial State for Channels Output (FTMx_OUTINIT) Addresses: FTM0_OUTINIT is 4003_8000h base + 5Ch offset = 4003_805Ch FTM1_OUTINIT is 4003_9000h base + 5Ch offset = 4003_905Ch FTM2_OUTINIT is 400B_8000h base + 5Ch offset = 400B_805Ch Reset...
Page 985 Chapter 41 FlexTimer (FTM) FTMx_OUTINIT field descriptions (continued) Field Description Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 2 Output Initialization Value CH2OI Selects the value that is forced into the channel output when the initialization occurs.
Page 986 Memory Map and Register Definition FTMx_OUTMASK field descriptions Field Description 31–8 This read-only field is reserved and always has the value zero. Reserved Channel 7 Output Mask CH7OM Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally).
Page 987 Chapter 41 FlexTimer (FTM) FTMx_OUTMASK field descriptions (continued) Field Description Channel 0 Output Mask CH0OM Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). Channel output is not masked. It continues to operate normally. Channel output is masked.
Page 988 Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field Description Synchronization Enable for n = 6 SYNCEN3 Enables PWM synchronization of registers C(n)V and C(n+1)V. The PWM synchronization in this pair of channels is disabled. The PWM synchronization in this pair of channels is enabled. Deadtime Enable for n = 6 DTEN3 Enables the deadtime insertion in the channels (n) and (n+1).
Page 989 Chapter 41 FlexTimer (FTM) FTMx_COMBINE field descriptions (continued) Field Description This read-only field is reserved and always has the value zero. Reserved Fault Control Enable for n = 4 FAULTEN2 Enables the fault control in channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. The fault control in this pair of channels is disabled.
Page 990 Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field Description The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Combine Channels for n = 4 COMBINE2 Enables the combine feature for channels (n) and (n+1).
Page 991 Chapter 41 FlexTimer (FTM) FTMx_COMBINE field descriptions (continued) Field Description The dual edge capture mode in this pair of channels is disabled. The dual edge capture mode in this pair of channels is enabled. Complement of Channel (n) for n = 2 COMP1 Enables complementary mode for the combined channels.
Page 992 Memory Map and Register Definition FTMx_COMBINE field descriptions (continued) Field Description Dual Edge Capture Mode Enable for n = 0 DECAPEN0 Enables the dual edge capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in dual edge capture mode according to Table 41-7.
Page 993 Chapter 41 FlexTimer (FTM) FTMx_DEADTIME field descriptions (continued) Field Description 7–6 Deadtime Prescaler Value DTPS Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter. This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide the system clock by 1.
Page 994 Memory Map and Register Definition Addresses: FTM0_EXTTRIG is 4003_8000h base + 6Ch offset = 4003_806Ch FTM1_EXTTRIG is 4003_9000h base + 6Ch offset = 4003_906Ch FTM2_EXTTRIG is 400B_8000h base + 6Ch offset = 400B_806Ch Reserved[bit 8] Reset Reserved[7:0] Reset FTMx_EXTTRIG field descriptions Field Description 31–8...
Page 995 Chapter 41 FlexTimer (FTM) FTMx_EXTTRIG field descriptions (continued) Field Description Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 4 Trigger Enable CH4TRIG Enable the generation of the channel trigger when the FTM counter is equal to the CnV register.
Page 996 Memory Map and Register Definition FTMx_POL field descriptions Field Description 31–8 This field is reserved. Reserved Channel 7 Polarity POL7 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high.
Page 997 Chapter 41 FlexTimer (FTM) FTMx_POL field descriptions (continued) Field Description The channel polarity is active high. The channel polarity is active low. Channel 0 Polarity POL0 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high.
Page 998 Memory Map and Register Definition FTMx_FMS field descriptions (continued) Field Description Fault Detection Flag FAULTF Represents the logic OR of the individual FAULTFj bits (where j = 3, 2, 1, 0). Clear FAULTF by reading the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition at the enabled fault inputs.
Page 999 Chapter 41 FlexTimer (FTM) FTMx_FMS field descriptions (continued) Field Description No fault condition was detected at the fault input. A fault condition was detected at the fault input. Fault Detection Flag 1 FAULTF1 Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault condition is detected at the fault input.
Page 1000 Memory Map and Register Definition Addresses: FTM0_FILTER is 4003_8000h base + 78h offset = 4003_8078h FTM1_FILTER is 4003_9000h base + 78h offset = 4003_9078h FTM2_FILTER is 400B_8000h base + 78h offset = 400B_8078h Reserved CH3FVAL CH2FVAL CH1FVAL CH0FVAL Reset FTMx_FILTER field descriptions Field Description 31–16...

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