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Memory map and register definition
12.3 Memory map and register definition
The SIM module contains many bitfields for selecting the clock source and dividers for
various module clocks.
The SIM registers can be written only in supervisor mode. In
user mode, write accesses are blocked and will result in a bus
error.
The SIM_SOPT1 and SIM_SOPT1CFG registers are located at
a different base address than the other SIM registers.
Absolute
address
(hex)
4004_7000
System Options Register 1 (SIM_SOPT1)
4004_7004
SOPT1 Configuration Register (SIM_SOPT1CFG)
4004_8004
System Options Register 2 (SIM_SOPT2)
4004_800C System Options Register 4 (SIM_SOPT4)
4004_8010
System Options Register 5 (SIM_SOPT5)
4004_8018
System Options Register 7 (SIM_SOPT7)
4004_8024
System Device Identification Register (SIM_SDID)
4004_8034
System Clock Gating Control Register 4 (SIM_SCGC4)
4004_8038
System Clock Gating Control Register 5 (SIM_SCGC5)
4004_803C System Clock Gating Control Register 6 (SIM_SCGC6)
4004_8040
System Clock Gating Control Register 7 (SIM_SCGC7)
4004_8044
System Clock Divider Register 1 (SIM_CLKDIV1)
4004_804C Flash Configuration Register 1 (SIM_FCFG1)
4004_8050
Flash Configuration Register 2 (SIM_FCFG2)
4004_8058
Unique Identification Register Mid-High (SIM_UIDMH)
4004_805C Unique Identification Register Mid Low (SIM_UIDML)
4004_8060
Unique Identification Register Low (SIM_UIDL)
4004_8100
COP Control Register (SIM_COPC)
4004_8104
Service COP (SIM_SRVCOP)
144
NOTE
NOTE
SIM memory map
Register name
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
Access
Reset value
(in bits)
32
R/W
See section
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R
See section
32
R/W
F000_0030h
32
R/W
0000_0182h
32
R/W
0000_0001h
32
R/W
0000_0100h
32
R/W
See section
32
R/W
See section
32
R
See section
32
R
See section
32
R
See section
32
R
See section
32
R/W
0000_000Ch
32
W
0000_0000h
Freescale Semiconductor, Inc.
Section/
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