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Memory map/register definition
36.4.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)
Address: Base address + Bh offset
Bit
7
Read
Write
Reset
0
Field
SSLT[7:0]
SSLT[7:0]
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
36.4.13 I2C Status register 2 (I2Cx_S2)
Address: Base address + Ch offset
Bit
7
Read
0
Write
Reset
0
Field
7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
5
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
4
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
3
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
1
Error flag
ERROR
Indicates if there are read or write errors with the Tx and Rx buffers.
0
The buffer is not full and all write/read operations have no errors.
1
There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set
and the buffer is busy).
626
6
5
0
0
I2Cx_SLTL field descriptions
6
5
0
0
0
0
I2Cx_S2 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4
3
SSLT[7:0]
0
0
Description
4
3
0
0
0
0
Description
2
1
0
0
2
1
0
ERROR
EMPTY
w1c
0
0
Freescale Semiconductor, Inc.
0
0
0
1
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