Block Diagram - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction
18.2.2.4 Debug mode
When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic
works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx
mode, the LLWU becomes inactive.

18.2.3 Block diagram

The following figure is the block diagram for the LLWU module.
Module7 interrupt flag
(LLWU_M7IF)
Module0 interrupt flag
(LLWU_M0IF)
FILT1[FILTSEL]
LLWU_P15
LLWU_P0
FILT2[FILTSEL]
266
WUME7
Interrupt module
flag detect
Interrupt module
flag detect
WUME0
LPO
Synchronizer
Pin filter 1
LPO
Pin filter 2
Synchronizer
WUPE15
2
Edge
detect
Edge
detect
2
WUPE0
Figure 18-1. LLWU block diagram
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
enter low leakge mode
LLWU_MWUF7 occurred
Internal
module
sources
LLWU_MWUF0 occurred
FILT1[FILTE]
Pin filter 1
wakeup
Edge occurred
LLWU
detect
controller
FILT2[FILTE]
Pin filter 2
wakeup
occurred
Edge
detect
LLWU_P15
wakeup occurred
External
pin sources
LLWU_P0
wakeup occurred
exit low leakge mode
interrupt flow
reset flow
Freescale Semiconductor, Inc.