Error Interrupt Status Register (Usbx_Errstat) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

33.5.7 Error Interrupt Status register (USBx_ERRSTAT)

Contains enable bits for each of the error sources within the USB Module. Each of these
bits are qualified with their respective error enable bits. All bits of this register are
logically OR'd together and the result placed in the ERROR bit of the ISTAT register.
After an interrupt bit has been set it may only be cleared by writing a one to the
respective interrupt bit. Each bit is set as soon as the error condition is detected.
Therefore, the interrupt does not typically correspond with the end of a token being
processed. This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 88h offset = 4007_2088h
Bit 7
Read BTSERR
Write w1c
Reset 0
Field
7 This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the error.
BTSERR
6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given
DMAERR the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit
data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB
module to minimize bus request and bus grant latency. This bit is also set if a data packet to or from the
host is larger than the buffer size allocated in the BDT. In this case the data packet is truncated as it is put
in buffer memory.
4 This bit is set when a bus turnaround timeout error occurs. The USB module contains a bus turnaround
BTOERR timer that keeps track of the amount of time elapsed between the token and data phases of a SETUP or
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted
from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
3 This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
DFN8 fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
2 This bit is set when a data packet is rejected due to a CRC16 error.
CRC16
1 This error interrupt has two functions. When the USB Module is operating in peripheral mode
CRC5 (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set
the token packet was rejected due to a CRC5 error.
0 This bit is set when the PID check field fails.
PIDERR
Freescale Semiconductor, Inc.
6 5
0 DMAERR BTOERR
w1c
0 0
USBx_ERRSTAT field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 33 Universal Serial Bus (USB) FS Subsystem
4 3
DFN8 CRC16
w1c w1c
0 0
Description
2 1
CRC5 PIDERR
w1c w1c
0 0
0
w1c
0
547