Platform Control Register (Mcm_Placr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present

16.2.3 Platform Control Register (MCM_PLACR)

The PLACR register selects the arbitration policy for the crossbar masters and configures
the flash memory controller.
The speculation buffer and cache in the flash memory controller is configurable via
PLACR[15:10 ].
The speculation buffer is enabled only for instructions after reset. It is possible to have
these states for the speculation buffer:
DFCS
0
0
1
The cache in flash controller is enabled and caching both instruction and data type fetches
after reset. It is possible to have these states for the cache:
DFCC
0
0
0
0
1
Freescale Semiconductor, Inc.
MCM_PLAMC field descriptions (continued)
0
1
X
DFCIC
0
0
1
1
X
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 16 Miscellaneous Control Module (MCM)
Description
EFDS
Speculation buffer is on for instruction
and off for data.
Speculation buffer is on for instruction
and on for data.
Speculation buffer is off.
DFCDA
0
1
0
1
X
Description
Description
Cache is on for both
instruction and data.
Cache is on for instruction
and off for data.
Cache is off for instruction
and on for data.
Cache is off for both
instruction and data.
Cache is off.
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