Timer Compare N Register (Flexio_Timcmpn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory Map and Registers
Field
5–4 Timer Stop Bit
TSTOP
The stop bit can be added on a timer compare (between each word) or on a timer disable. When stop bit is
enabled, configured shifters will output the contents of the stop bit when the timer is disabled. When stop
bit is enabled on timer disable, the timer remains disabled until the next rising edge of the shift clock. If
configured for both timer compare and timer disable, only one stop bit is inserted on timer disable.
00 Stop bit disabled
01 Stop bit is enabled on timer compare
10 Stop bit is enabled on timer disable
11 Stop bit is enabled on timer compare and timer disable
3–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Timer Start Bit
TSTART
When start bit is enabled, configured shifters will output the contents of the start bit when the timer is
enabled and the timer counter will reload from the compare register on the first rising edge of the shift
clock.
0 Start bit disabled
1 Start bit enabled
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

39.3.19 Timer Compare N Register (FLEXIO_TIMCMPn)

.
Address: 4005_F000h base + 500h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Field
31–16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
CMP Timer Compare Value
The timer compare value is loaded into the timer counter when the timer is first enabled, when the timer is
reset and when the timer decrements down to zero. In dual 8-bit counters baud/bit mode, the lower 8-bits
configures the baud rate divider equal to (CMP[7:0] + 1) * 2. The upper 8-bits configure the number of bits
in each word equal to (CMP[15:8] + 1) / 2. In dual 8-bit counters PWM mode, the lower 8-bits configure the
high period of the output to (CMP[7:0] + 1) and the upper 8-bits configure the low period of the output to
(CMP[15:8] + 1). In 16-bit counter mode, the compare value can be used to generate the baud rate divider
(if shift clock source is timer output) to equal (CMP[15:0] + 1) * 2. When the shift clock source is a pin or
766
FLEXIO_TIMCFGn field descriptions (continued)
25 24 23 22 21 20 19 18
0
0 0 0 0 0 0 0 0
FLEXIO_TIMCMPn field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17 16 15 14 13 12 11 10
0 0 0 0 0 0 0 0
Description
9 8 7 6 5 4 3 2
CMP
0 0 0 0 0 0 0 0
Freescale Semiconductor, Inc.
1 0
0 0