Shifter Error Register (Flexio_Shifterr); Timer Status Register (Flexio_Timstat) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Memory Map and Registers

39.3.5 Shifter Error Register (FLEXIO_SHIFTERR)

.
Address: 4005_F000h base + 14h offset = 4005_F014h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–4
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
SEF
Shifter Error Flags
The shifter error flag is set when one of the following events occurs:
For SMOD=Receive, indicates Shifter was ready to store new data into SHIFTBUF before the previous
data was read from SHIFTBUF (SHIFTBUF Overrun), or indicates that the received start or stop bit does
not match the expected value.
For SMOD=Transmit, indicates Shifter was ready to load new data from SHIFTBUF before new data had
been written into SHIFTBUF (SHIFTBUF Underrun).
For SMOD=Match Store, indicates a match event occured before the previous match data was read from
SHIFTBUF (SHIFTBUF Overrun).
For SMOD=Match Continuous, the error flag is set when a match has occured between SHIFTBUF and
Shifter.
Can be cleared by writing logic one to the flag. For SMOD=Match Continuous, can also be cleared when
the SHIFTBUF register is read.
0
Shifter Error Flag is clear
1
Shifter Error Flag is set

39.3.6 Timer Status Register (FLEXIO_TIMSTAT)

.
Address: 4005_F000h base + 18h offset = 4005_F018h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
754
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
FLEXIO_SHIFTERR field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
2
1
0
SEF
w1c
0
0
0
2
1
0
TSF
w1c
0
0
0

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