Block Diagram; Modes Of Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

40.2.2 Block diagram

The following block diagram also shows the module clocks.
Bus
Clock
Audio
Clock
Bus
Clock

40.2.3 Modes of operation

The module operates in these power modes: Run mode, stop modes, low-leakage modes,
and Debug mode.
40.2.3.1 Run mode
In Run mode, the SAI transmitter and receiver operate normally.
40.2.3.2 Stop modes
In Stop mode, the SAI transmitter and/or receiver can continue operating provided the
appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively),
and provided the transmitter and/or receiver is/are using an externally generated bit clock
or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter
and/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.
Freescale Semiconductor, Inc.
Write
FIFO
FIFO
Control
Control
Registers
Transmitter
Receiver
Control
Registers
Read
FIFO FIFO
Control
2
Figure 40-1. I S/SAI block diagram
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 40 Synchronous Audio Interface (SAI)
Read
Shift
FIFO
Register
Control
Bit
Clock
Frame
Bit Clock
Sync
Generation
Control
Synchronous Mode
Frame
Bit Clock
Sync
Generation
Control
Bit
Clock
Write
Shift
FIFO
Register
Control
SAI_TX_DATA
SAI_TX_BCLK
SAI_TX_SYNC
SAI_RX_SYNC
SAI_RX_BCLK
SAI_RX_DATA
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