Dac Control Register 1 (Dacx_C1); Dac Control Register 2 (Dacx_C2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definition

25.4.5 DAC Control Register 1 (DACx_C1)

Address: 4003_F000h base + 22h offset = 4003_F022h
Bit 7
Read
DMAEN
Write
Reset
0
Field
7 DMA Enable Select
DMAEN
0 DMA is disabled.
1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
interrupts will not be presented on this module at the same time.
6–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2–1 DAC Buffer Work Mode Select
DACBFMD
00 Normal mode
01 Reserved
10 One-Time Scan mode
11 FIFO mode
0 DAC Buffer Enable
DACBFEN
0 Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means
converted data can be from any word of the buffer.

25.4.6 DAC Control Register 2 (DACx_C2)

Address: 4003_F000h base + 23h offset = 4003_F023h
Bit 7
Read
Write
Reset 0
Field
7–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
418
6 5
0
0 0
DACx_C1 field descriptions
6 5
0
DACBFRP
0 0
DACx_C2 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4 3
0 0
Description
4 3
0 0
Description
2 1
DACBFMD DACBFEN
0 0
2 1
0
DACBFUP
0 0
Freescale Semiconductor, Inc.
0
0
0
1