Port Toggle Output Register (Gpiox_Ptor); Port Data Input Register (Gpiox_Pdir) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Writing to this register will update the contents of the corresponding bit in the Port Data Output Register

(PDOR) as follows:

Corresponding bit in PDORn does not change.

Corresponding bit in PDORn is cleared to logic 0.

41.3.4 Port Toggle Output Register (GPIOx_PTOR)

Address: Base address + Ch offset

Port Toggle Output

Writing to this register will update the contents of the corresponding bit in the PDOR as follows:

Corresponding bit in PDORn does not change.

Corresponding bit in PDORn is set to the inverse of its existing logic state.

Do not modify pin configuration registers associated with pins

not available in your selected package. All unbonded pins not

available in your package will default to DISABLE state for

lowest power consumption.

Address: Base address + 10h offset

Freescale Semiconductor, Inc.

GPIOx_PCOR field descriptions (continued)

GPIOx_PTOR field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 41 General-Purpose Input/Output (GPIO)