Counter (Tpmx_Cnt) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory Map and Register Definition
Field
0 TPM counter has not overflowed.
1 TPM counter has overflowed.
6 Timer Overflow Interrupt Enable
TOIE
Enables TPM overflow interrupts.
0 Disable TOF interrupts. Use software polling or DMA request.
1 Enable TOF interrupts. An interrupt is generated when TOF equals one.
5 Center-Aligned PWM Select
CPWMS
Selects CPWM mode. This mode configures the TPM to operate in up-down counting mode.
This field is write protected. It can be written only when the counter is disabled.
0 TPM counter operates in up counting mode.
1 TPM counter operates in up-down counting mode.
4–3 Clock Mode Selection
CMOD
Selects the TPM counter clock modes. When disabling the counter, this field remain set until
acknolwedged in the TPM clock domain.
00 TPM counter is disabled
01 TPM counter increments on every TPM counter clock
10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
11 Reserved.
PS Prescale Factor Selection
Selects one of 8 division factors for the clock mode selected by CMOD.
This field is write protected. It can be written only when the counter is disabled.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128

29.4.2 Counter (TPMx_CNT)

The CNT register contains the TPM counter value.
Reset clears the CNT register. Writing any value to COUNT also clears the counter.
When debug is active, the TPM counter does not increment unless configured otherwise.
Reading the CNT register adds two wait states to the register access due to
synchronization delays.
464
TPMx_SC field descriptions (continued)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
Freescale Semiconductor, Inc.