Overview; Features; Modes Of Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Introduction

26.1.1 Overview

The Voltage Reference provides a buffered reference voltage for use as an external

reference. In addition, the buffered reference is available internally for use with on chip

peripherals such as ADCs and DACs. Refer to the chip configuration details for a

description of these options. The reference voltage signal is output on a dedicated output

pin when the VREF is enabled. The Voltage Reference output can be trimmed with a

resolution of 0.5mV by means of the TRM register TRIM[5:0] bitfield.

The Voltage Reference has the following features:

• Programmable trim register with 0.5 mV steps, automatically loaded with factory

trimmed value upon reset

• Programmable buffer mode selection:

• Bandgap enabled/standby (output buffer disabled)

• Low power buffer mode (output buffer enabled)

• High power buffer mode (output buffer enabled)

• 1.2 V output at room temperature

• Dedicated output pin, VREF_OUT

The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The

Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait

(VLPW) and Very Low Power Stop (VLPS). If it is desired to use the VREF regulator

and/or the chop oscillator in the very low power modes, the system reference voltage

(also referred to as the bandgap voltage reference) must be enabled in these modes. Refer

to the chip configuration details for information on enabling this mode of operation.

Having the VREF regulator enabled does increase current consumption. In very low

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.