I2C Address Register 2 (I2Cx_A2); I2C Scl Low Timeout Register High (I2Cx_Slth) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
1 SCL High Timeout Flag 2
SHTF2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue / 512. Software clears
this bit by writing 1 to it.
0 No SCL high and SDA low timeout occurs
1 SCL high and SDA low timeout occurs
0 SHTF2 Interrupt Enable
SHTF2IE
Enables SCL high and SDA low timeout interrupt.
0 SHTF2 interrupt is disabled
1 SHTF2 interrupt is enabled

36.4.10 I2C Address Register 2 (I2Cx_A2)

Address: Base address + 9h offset
Bit 7
Read
Write
Reset
1
Field
7–1 SMBus Address
SAD
Contains the slave address used by the SMBus. This field is used on the device default address or other
related addresses.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

36.4.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)

Address: Base address + Ah offset
Bit 7
Read
Write
Reset 0
Field
SSLT[15:8] SSLT[15:8]
Most significant byte of SCL low timeout value that determines the timeout period of SCL low.
Freescale Semiconductor, Inc.
I2Cx_SMB field descriptions (continued)
6 5
1 0
I2Cx_A2 field descriptions
6 5
0 0
I2Cx_SLTH field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 36 Inter-Integrated Circuit (I2C)
Description
4 3
SAD
0 0
Description
4 3
SSLT[15:8]
0 0
Description
2 1
0 1
2 1
0 0
0
0
0
0
0
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