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Module operation in low-power modes
7.5 Module operation in low-power modes
The table found here illustrates the functionality of each module while the chip is in each
of the low power modes.
The standard behavior is shown with some exceptions for Compute Operation (CPO) and
Partial Stop2 (PSTOP2).
Debug modules are discussed separately; see
ratings (such as 4 MHz and 1 Mbit/s) represent the maximum frequencies or maximum
data rates per mode. Following is list of terms also used in the table.
• FF = Full functionality. In VLPR and VLPW, the system frequency is limited, but if
a module does not have a limitation in its functionality, it is still listed as FF.
• Async operation = Fully functional with alternate clock source, provided the selected
clock source remains enabled
• static = Module register states and associated memories are retained.
• powered = Memory is powered to retain contents.
• low power = Memory is powered to retain contents in a lower power state
• OFF = Modules are powered off; module is in reset state upon wake-up. For clocks,
OFF means disabled.
• wakeup = Modules can serve as a wake-up source for the chip.
Table 7-2. Module operation in low power modes
Modules
VLPR
NVIC
FF
Mode Controller
FF
1
LLWU
static
Regulator
low power
LVD
disabled
Brown-out
ON
Detection
DMA
FF
Async operation
in CPO
96
VLPW
Core modules
FF
System modules
FF
static
low power
disabled
ON
FF
Async operation Async operation
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Debug in low-power
Stop
VLPS
static
static
FF
FF
static
static
ON
low power
ON
disabled
ON
ON
modes. Number
LLS
VLLSx
static
OFF
FF
FF
2
FF
FF
low power
low power in
VLLS3, OFF in
VLLS0/1
disabled
disabled
ON
ON in VLLS1/3,
optionally
disabled in
3
VLLS0
static
OFF
Freescale Semiconductor, Inc.
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