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Memory map/register description
Address: 4003_7000h base + E4h offset = 4003_70E4h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
LTL
Life Timer value
Shows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read.
30.4.4 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Access: User read/write
Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
TSV
Timer Start Value
Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt and
load this register value again. Writing a new value to this register will not restart the timer; instead the
value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new
value, the timer must be disabled and enabled again.
30.4.5 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Access: User read only
Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 1d
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
492
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
PIT_LTMR64L field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
PIT_LDVALn field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
LTL
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
TSV
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
TVL
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
1
0
0
0
1
0
0
0
1
0
0
0
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