Adc0 Connections/Channel Assignment - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Chip-specific ADC information

23.1.2 DMA Support on ADC

Applications may require continuous sampling of the ADC that may have considerable

load on the CPU. The ADC supports DMA request functionality for higher performance

when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA

req) on conversion completion.

23.1.3 ADC0 connections/channel assignment

As indicated by the following sections, each ADCx_DPx input

and certain ADCx_DMx inputs may operate as single-ended

ADC channels in single-ended mode.

(SC1n[ADCH])

Table 23-2. ADC0 channel assignment

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Input signal (SC1n[DIFF]=

ADC0_DP0 and ADC0_DM0

ADC0_DP1 and ADC0_DM1

ADC0_DP2 and ADC0_DM2

ADC0_DP3 and ADC0_DM3

Input signal (SC1n[DIFF]=

ADC0_DP0/ADC0_SE0

ADC0_DP1/ADC0_SE1

ADC0_DP2/ADC0_SE2

ADC0_DP3/ADC0_SE3

ADC0_DM0/ADC0_SE4a

ADC0_DM1/ADC0_SE5a

ADC0_DM2/ADC0_SE6a

ADC0_DM3/ADC0_SE7a

Freescale Semiconductor, Inc.