Table of Contents
Advertisement
Functional description
Figure 35-5. SPIH:L write side structural overview in FIFO mode
35.5.5 SPI Transmission by DMA
SPI supports both Transmit and Receive by DMA. The basic flow of SPI transmission by
DMA is as below.
Figure 35-6. Basic Flow of SPI Transmission by DMA
592
Read Access
SPI Data Register
spidh:l_tx_reg
FIFO Ctrlr
Read
shfr_tx_reg
Control
RESET
Configure DMA Controller
for SPI Transmission
Configure SPI before Transmission
Set TXDMAE/RXDMAE=1 to enable
Transmit/Receive by DMA
Set SPE=1 to start transmission in
master mode or enable SPI for
transmission in slave moe
Wait for interrupt(s) of DMA Controller
indicating end of SPI transmission
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
IPBus (ips_rdata[7:0])
SPI_REG_BLOCK
TX- FIFO
FIFO depth = 8 bytes
SPI_CORE_SHFR
Freescale Semiconductor, Inc.
Advertisement
Table of Contents
