Osc Memory Map/Register Definition - NXP Semiconductors MKL27Z128VFM4 Reference Manual

OSC Memory Map/Register Definition

28.8.1 OSC Memory Map/Register Definition
Absolute
address
(hex)
4006_5000 OSC Control Register (OSC0_CR)
28.8.1.1 OSC Control Register (OSCx_CR)
After OSC is enabled and starts generating the clocks, the
configurations such as low power and frequency range, must
not be changed.
Address: 4006_5000h base + 0h offset = 4006_5000h
Bit 7
Read
ERCLKEN
Write
Reset 0
Field
7 External Reference Enable
ERCLKEN
Enables external reference clock (OSCERCLK) .
0 External reference clock is inactive.
1 External reference clock is enabled.
6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 External Reference Stop Enable
EREFSTEN
Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters
Stop mode.
0 External reference clock is disabled in Stop mode.
1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
3 Oscillator 2 pF Capacitor Load Configure
SC2P
448
OSC memory map
Register name
NOTE
6 5
0
EREFSTEN
0 0
OSCx_CR field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
Access
(in bits)
8 R/W
4 3
0
SC2P SC4P
0 0
Description
Section/
Reset value
page
28.8.1.1/
00h
448
2 1
SC8P SC16P
0 0
Freescale Semiconductor, Inc.
0
0