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Modes of operation
• 32-bit prefetch speculation buffer for program flash accesses with controls for
instruction/data access
• 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen
32-bit entries with invalidation control
44.2 Modes of operation
The FMC operates only when a bus master accesses the program flash memory.
In terms of chip power modes:
• The FMC operates only in Run and Wait modes, including VLPR and VLPW modes.
• For any power mode where the program flash memory cannot be accessed, the FMC
is disabled.
44.3 External signal description
The FMC has no external (off-chip) signals.
44.4 Memory map and register descriptions
The MCM's programming model provides control and configuration of the FMC's
features.
For details, see the description of the MCM's Platform Control Register (PLACR).
44.5 Functional description
The FMC is a flash acceleration unit with flexible buffers for user configuration.
Besides managing the interface between bus masters and the program flash memory, the
FMC can be used to customize the program flash memory cache and buffer to provide
single-cycle system clock data access times. Whenever a hit occurs for the prefetch
speculation buffer or the cache (when enabled), the requested data is transferred within a
single system clock.
Upon system reset, the FMC is configured as follows:
• Flash cache is enabled.
• Instruction speculation and caching are enabled.
884
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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