Cop Control Register (Sim_Copc) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition

12.3.18 COP Control Register (SIM_COPC)

All of the bits in this register can be written only once after a reset, writing this register
will also reset the COP counter.
Address: 4004_7000h base + 1100h offset = 4004_8100h
Bit 31 30 29
R
W
Reset 0 0 0
15 14 13
Bit
R
W
Reset 0 0 0
Field
31–8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
7–6 COP Clock Select
COPCLKSEL
This write-once field selects the clock source of the COP watchdog.
00 LPO clock (1 kHz)
01 MCGIRCLK
10 OSCERCLK
11 Bus clock
5 COP Debug Enable
COPDBGEN
0 COP is disabled and the counter is reset in Debug mode
1 COP is enabled in Debug mode
4 COP Stop Enable
COPSTPEN
0 COP is disabled and the counter is reset in Stop modes
1 COP is enabled in Stop modes
3–2 COP Watchdog Timeout
COPT
This write-once field selects the timeout period of the COP. COPT along with the COPCLKS field define
the COP timeout period.
00 COP disabled
168
28 27 26 25
0 0 0 0
12 11 10 9
0
0 0 0 0
SIM_COPC field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24 23 22 21
0
0 0 0 0
8 7 6 5
COPCLKSEL
0 0 0 0
Description
20 19 18 17
0 0 0 0
4 3 2 1
COPT
0 1 1 0
Freescale Semiconductor, Inc.
16
0
0
0