Counter; Reference Clock Pin Requirements; Reset - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Chapter 28 Oscillator (OSC)

28.9.2.3 High-Frequency, High-Gain Mode

In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier.

The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass

frequency filtering as well as hysteresis for voltage filtering and converts the output to

logic levels.

28.9.2.4 High-Frequency, Low-Power Mode

In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize

power consumption. As the oscillation amplitude increases, the amplifier current is

reduced. This continues until a desired amplitude is achieved at steady-state. In this

mode, no external resistor should be used.

The oscillator input buffer in this mode is differential. It provides low pass frequency

filtering as well as hysteresis for voltage filtering and converts the output to logic levels.

28.9.3 Counter

The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected

4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter

passes XTL_CLK onto OSC_CLK_OUT. This counting timeout is used to guarantee

output clock stability.

The OSC module requires use of both the EXTAL and XTAL pins to generate an output

clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The

EXTAL and XTAL pins are available for I/O. For the implementation of these pins on

this device, refer to the Signal Multiplexing chapter.

There is no reset state associated with the OSC module. The counter logic is reset when

the OSC is not configured to generate clocks.

There are no sources of reset requests for the OSC module.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.