Mcg Status Register (Mcg_S); Mcg Status And Control Register (Mcg_Sc) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

27.2.3 MCG Status Register (MCG_S)

Address: 4006_4000h base + 6h offset = 4006_4006h
Bit 7
Read
Write
Reset 0
Field
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
3–2 Clock Mode Status
CLKST
Indicates the current clock mode. This field does not update immediately after a write to MCG_C1[CLKS]
due to internal synchronization between clock domains.
00 HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.
01 LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.
10 External clock is selected as the main clock source, and MCG_Lite works at EXT mode.
11 Reserved.
1 OSC Initialization Status
OSCINIT0
This flag, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock are
completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the Oscillator
(OSC) chapter for more information.
0 OSC is not ready.
1 OSC clock is ready.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

27.2.4 MCG Status and Control Register (MCG_SC)

Address: 4006_4000h base + 8h offset = 4006_4008h
Bit 7
Read
Write
Reset
0
Field
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
Freescale Semiconductor, Inc.
6 5
0
0 0
MCG_S field descriptions
6 5
0
0 0
MCG_SC field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite)
4 3
CLKST
0 0
Description
4 3
FCRDIV
0 0
Description
2 1
OSCINIT0
1 0
2 1
0 0
0
0
0
0
0
0
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