Power Modes - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description
24.4.1.4 Sampled, Filtered mode (#s 4B)
In Sampled, Filtered mode, the analog comparator block is powered and active. The path
from analog inputs to COUTA is combinational unclocked. Windowing control is
completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter
block clock input.
EN, PMODE, HYSTCTR[1:0
INP
INM
bus clock
Figure 24-5. Sampled, Filtered (# 4B): sampling point internally derived
The only difference in operation between Sampled, Non-Filtered (# 3B) and Sampled,
Filtered (# 4B) is that now, CR0[FILTER_CNT]>1, which activates filter operation.

24.4.2 Power modes

24.4.2.1 Wait mode operation
During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and
a CMP interrupt can wake the MCU.
406
Internal bus
FILT_PER FILT_PER
] COS INV
+
+
Polarity
select
-
-
CMPO
WINDOW/SAMPLE
Clock
prescaler
divided
bus
clock
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
OPE
COUT
WE
SE
FILTER_CNT
>
0x01
0
0
Filter
Window
block
control
1
0
COUTA
CGMUX
SE=0
IER/F CFR/F
Interrupt
control
IRQ
COUT
To other SOC functions
0
CMPO to
1
PAD
COS
Freescale Semiconductor, Inc.