External Signal Description; Memory Map/Register Definition; Channel Configuration Register (Dmamuxx_Chcfgn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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In this mode, the DMA channel is disabled. Because disabling and enabling of DMA

channels is done primarily via the DMA configuration registers, this mode is used

mainly as the reset state for a DMA channel in the DMA channel MUX. It may also

be used to temporarily suspend a DMA channel while reconfiguration of the system

takes place, for example, changing the period of a DMA trigger.

• Normal mode

In this mode, a DMA source is routed directly to the specified DMA channel. The

operation of the DMAMUX in this mode is completely transparent to the system.

• Periodic Trigger mode

In this mode, a DMA source may only request a DMA transfer, such as when a

transmit buffer becomes empty or a receive buffer becomes full, periodically.

Configuration of the period is done in the registers of the periodic interrupt timer

(PIT). This mode is available only for channels 0–1.

20.3 External signal description

The DMAMUX has no external pins.

This section provides a detailed description of all memory-mapped registers in the

Channel Configuration register (DMAMUX0_CHCFG0)

Channel Configuration register (DMAMUX0_CHCFG1)

Channel Configuration register (DMAMUX0_CHCFG2)

Channel Configuration register (DMAMUX0_CHCFG3)

Each of the DMA channels can be independently enabled/disabled and associated with

one of the DMA slots (peripheral slots or always-on slots) in the system.

Freescale Semiconductor, Inc.

DMAMUX memory map

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 20 Direct Memory Access Multiplexer (DMAMUX)