Memory Map And Register Definition; Mtb_Ram Memory Map - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Memory map and register definition

In addition, there are two signals formed by the MTB_DWT module and driven to the

MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can

be configured using the trace watchpoints to define programmable addresses and data

values to affect the program trace recording state.

43.3 Memory map and register definition

The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB

address space for their programming models. For each address space, there are a variety

of control and configurable registers near the base address, followed by a large unused

address space and finally a set of CoreSight registers to support dynamic determination of

the debug configuration for the device.

Accesses to the programming model follow standard ARM conventions. Taken from the

ARM CoreSight Micro Trace Buffer documentation, these are:

• Do not attempt to access reserved or unused address locations. Attempting to access

these locations can result in UNPREDICTABLE behavior.

• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN

reset values are not programmed prior to enabling trace.

• Unless otherwise stated in the accompanying text:

• Do not modify reserved register bits

• Ignore reserved register bits on reads

• All register bits are reset to a logic 0 by a system or power-on reset

• Use only word size, 32-bit, transactions to access all registers

MTB Position Register (MTB_POSITION)

MTB Master Register (MTB_MASTER)

MTB Flow Register (MTB_FLOW)

F000_000C MTB Base Register (MTB_BASE)

Integration Mode Control Register (MTB_MODECTRL)

MTB memory map

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.