Sai Receive Configuration 5 Register (I2Sx_Rcr5); Sai Receive Data Register (I2Sx_Rdrn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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40.4.12 SAI Receive Configuration 5 Register (I2Sx_RCR5)

This register must not be altered when RCSR[RE] is set.

Address: 4002_F000h base + 94h offset = 4002_F094h

This field is reserved.

This read-only field is reserved and always has the value 0.

Word N Width

Configures the number of bits in each word, for each word except the first in the frame. The value written

must be one less than the number of bits per word. Word width of less than 8 bits is not supported.

This field is reserved.

This read-only field is reserved and always has the value 0.

Word 0 Width

Configures the number of bits in the first word in each frame. The value written must be one less than the

number of bits in the first word. Word width of less than 8 bits is not supported if there is only one word per

This field is reserved.

This read-only field is reserved and always has the value 0.

First Bit Shifted

Configures the bit index for the first bit received for each word in the frame. If configured for MSB First, the

index of the next bit received is one less than the current bit received. If configured for LSB First, the index

of the next bit received is one more than the current bit received. The value written must be greater than or

equal to the word width when configured for MSB First. The value written must be less than or equal to 31-

word width when configured for LSB First.

This field is reserved.

This read-only field is reserved and always has the value 0.

Reading this register introduces one additional peripheral clock wait state on each read.

Address: 4002_F000h base + A0h offset + (4d × i), where i=0d to 0d

Freescale Semiconductor, Inc.

I2Sx_RCR5 field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 40 Synchronous Audio Interface (SAI)