Modes Of Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction
• Receive data register full
• Receive overrun, parity error, framing error, and noise error
• Idle receiver detect
• Active edge on receive pin
• Break detect supporting LIN
• Receive data match
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity

37.2.2 Modes of operation

37.2.2.1 Stop mode
The LPUART will remain functional during Stop mode, provided the asynchronous
transmit and receive clock remains enabled. The LPUART can generate an interrupt or
DMA request to cause a wakeup from Stop mode.
37.2.2.2 Wait mode
The LPUART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
The transmitter and receiver will finish transmitting/receiving the current word.
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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.