NXP Semiconductors KL25 Series Reference Manual

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KL25 Sub-Family Reference Manual

Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4,

MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4,

MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4,

MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4

Document Number: KL25P80M48SF0RM

Rev. 3, September 2012

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Page 1 KL25 Sub-Family Reference Manual Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4, MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4, MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4 Document Number: KL25P80M48SF0RM Rev. 3, September 2012...
Page 2 KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Contents Section number Title Page Chapter 1 About This Document Overview..................................33 1.1.1 Purpose.................................33 1.1.2 Audience..............................33 Conventions..................................33 1.2.1 Numbering systems............................33 1.2.2 Typographic notation...........................34 1.2.3 Special terms..............................34 Chapter 2 Introduction Overview..................................35 Kinetis L Series................................35 KL25 Sub-Family Introduction.............................38 Module functional categories............................39 2.4.1 ARM® Cortex™-M0+ Core Modules......................39 2.4.2 System Modules............................40 2.4.3...
Page 4 Section number Title Page Module to Module Interconnects..........................45 3.2.1 Module to Module Interconnects.........................45 3.2.2 Analog reference options..........................48 Core Modules................................48 3.3.1 ARM Cortex-M0+ Core Configuration.......................48 3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration..............51 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............55 System Modules................................56 3.4.1 SIM Configuration............................56 3.4.2...
Page 5 Section number Title Page 3.6.3 SRAM Configuration...........................75 Analog...................................77 3.7.1 16-bit SAR ADC Configuration........................77 3.7.2 CMP Configuration............................81 3.7.3 12-bit DAC Configuration...........................83 Timers...................................84 3.8.1 Timer/PWM Module Configuration......................84 3.8.2 PIT Configuration............................87 3.8.3 Low-power timer configuration........................88 3.8.4 RTC configuration............................90 Communication interfaces............................91 3.9.1 Universal Serial Bus (USB) FS Subsystem....................91 3.9.2 SPI configuration............................96 3.9.3...
Page 6 Section number Title Page 4.6.3 Modules Restricted Access in User Mode....................112 Private Peripheral Bus (PPB) memory map........................112 Chapter 5 Clock Distribution Introduction...................................115 Programming model..............................115 High-Level device clocking diagram..........................115 Clock definitions................................116 5.4.1 Device clock summary..........................117 Internal clocking requirements.............................119 5.5.1 Clock divider values after reset........................119 5.5.2 VLPR mode clocking...........................120 Clock Gating.................................121...
Page 7 Section number Title Page 6.2.5 Debug resets..............................133 Boot....................................134 6.3.1 Boot sources..............................134 6.3.2 FOPT boot options............................134 6.3.3 Boot sequence..............................135 Chapter 7 Power Management Introduction...................................137 Clocking Modes................................137 7.2.1 Partial Stop..............................137 7.2.2 DMA Wakeup..............................138 7.2.3 Compute Operation............................139 7.2.4 Peripheral Doze............................140 7.2.5 Clock Gating..............................141 Power modes.................................141 Entering and exiting power modes..........................143 Module Operation in Low Power Modes........................143...
Page 8 Section number Title Page Debug Resets................................156 Micro Trace Buffer (MTB)............................157 Debug in Low Power Modes............................157 Debug & Security.................................157 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................159 10.2 Signal Multiplexing Integration............................159 10.2.1 Port control and interrupt module features....................160 10.2.2 Clock gating..............................161 10.2.3 Signal multiplexing constraints........................161 10.3...
Page 9 Section number Title Page 11.2.2 Modes of operation............................176 11.3 External signal description............................176 11.4 Detailed signal description............................177 11.5 Memory map and register definition..........................177 11.5.1 Pin Control Register n (PORTx_PCRn).......................183 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................185 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................186 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)....................186 11.6...
Page 10 Section number Title Page 12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...................211 12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...................213 12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)................213 12.2.16 Unique Identification Register Mid Low (SIM_UIDML)................214 12.2.17 Unique Identification Register Low (SIM_UIDL)..................214 12.2.18 COP Control Register (SIM_COPC)......................215 12.2.19 Service COP Register (SIM_SRVCOP)......................216 12.3...
Page 11 Section number Title Page 14.3 Low-voltage detect (LVD) system..........................237 14.3.1 LVD reset operation.............................238 14.3.2 LVD interrupt operation..........................238 14.3.3 Low-voltage warning (LVW) interrupt operation..................238 14.4 I/O retention..................................239 14.5 Memory map and register descriptions.........................239 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)............240 14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)............241 14.5.3...
Page 12 Section number Title Page 15.4.2 VLLS modes..............................263 15.4.3 Initialization..............................263 Chapter 16 Reset Control Module (RCM) 16.1 Introduction...................................265 16.2 Reset memory map and register descriptions.......................265 16.2.1 System Reset Status Register 0 (RCM_SRS0)....................265 16.2.2 System Reset Status Register 1 (RCM_SRS1)....................267 16.2.3 Reset Pin Filter Control register (RCM_RPFC)..................268 16.2.4 Reset Pin Filter Width register (RCM_RPFW)...................269 Chapter 17...
Page 13 Section number Title Page 18.2.3 Platform Control Register (MCM_PLACR)....................293 18.2.4 Compute Operation Control Register (MCM_CPO)...................296 Chapter 19 Micro Trace Buffer (MTB) 19.1 Introduction...................................299 19.1.1 Overview..............................299 19.1.2 Features................................302 19.1.3 Modes of Operation.............................303 19.2 External Signal Description............................303 19.3 Memory Map and Register Definition..........................304 19.3.1 MTB_RAM Memory Map...........................304 19.3.2...
Page 14 Section number Title Page Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 22.1 Introduction...................................337 22.1.1 Overview..............................337 22.1.2 Features................................338 22.1.3 Modes of operation............................338 22.2 External signal description............................339 22.3 Memory map/register definition...........................339 22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)................339 22.4 Functional description..............................340 22.4.1 DMA channels with periodic triggering capability..................341 22.4.2 DMA channels with no triggering capability....................343 22.4.3...
Page 15 Section number Title Page 23.4.2 Channel Initialization and Startup........................361 23.4.3 Dual-Address Data Transfer Mode......................363 23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................364 23.4.5 Termination..............................365 Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction...................................367 24.1.1 Features................................367 24.1.2 Modes of Operation.............................370 24.2 External Signal Description............................371 24.3 Memory Map/Register Definition..........................371 24.3.1...
Page 16 Section number Title Page 24.4.3 MCG Internal Reference Clocks........................388 24.4.4 External Reference Clock..........................389 24.4.5 MCG Fixed frequency clock ........................389 24.4.6 MCG PLL clock ............................390 24.4.7 MCG Auto TRIM (ATM)..........................390 24.5 Initialization / Application information........................391 24.5.1 MCG module initialization sequence......................391 24.5.2 Using a 32.768 kHz reference........................393 24.5.3 MCG mode switching..........................394...
Page 17 Section number Title Page Chapter 26 Flash Memory Controller (FMC) 26.1 Introduction...................................415 26.1.1 Overview..............................415 26.1.2 Features................................415 26.2 Modes of operation...............................416 26.3 External signal description............................416 26.4 Memory map and register descriptions.........................416 26.5 Functional description..............................416 Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction...................................419 27.1.1 Features................................420...
Page 18 Section number Title Page 27.4.8 Flash Command Operations.........................435 27.4.9 Margin Read Commands..........................440 27.4.10 Flash Command Description........................441 27.4.11 Security................................454 27.4.12 Reset Sequence............................456 Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Introduction...................................457 28.1.1 Features................................457 28.1.2 Block diagram..............................458 28.2 ADC Signal Descriptions..............................459 28.2.1 Analog Power (VDDA)..........................460 28.2.2 Analog Ground (VSSA)..........................460 28.2.3...
Page 19 Section number Title Page 28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............476 28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............477 28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............477 28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............478 28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............478 28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).............479 28.3.19...
Page 20 Section number Title Page 28.5 Initialization information..............................499 28.5.1 ADC module initialization example......................499 28.6 Application information..............................501 28.6.1 External pins and routing..........................501 28.6.2 Sources of error............................503 Chapter 29 Comparator (CMP) 29.1 Introduction...................................509 29.2 CMP features................................509 29.3 6-bit DAC key features..............................510 29.4 ANMUX key features..............................511 29.5 CMP, DAC and ANMUX diagram..........................511 29.6...
Page 21 Section number Title Page 29.13 DAC functional description............................535 29.13.1 Voltage reference source select........................535 29.14 DAC resets..................................535 29.15 DAC clocks...................................535 29.16 DAC interrupts................................536 29.17 CMP Trigger Mode...............................536 Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.1 Introduction...................................537 30.2 Features..................................537 30.3 Block diagram................................537 30.4 Memory map/register definition...........................539 30.4.1 DAC Data Low Register (DACx_DATnL)....................539...
Page 22 Section number Title Page 31.1.4 Block Diagram.............................548 31.2 TPM Signal Descriptions..............................549 31.2.1 TPM_EXTCLK — TPM External Clock....................549 31.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................550 31.3 Memory Map and Register Definition..........................550 31.3.1 Status and Control (TPMx_SC)........................552 31.3.2 Counter (TPMx_CNT)..........................553 31.3.3 Modulo (TPMx_MOD)..........................554 31.3.4 Channel (n) Status and Control (TPMx_CnSC)...................555...
Page 23 Section number Title Page 32.2 Signal description................................574 32.3 Memory map/register description..........................575 32.3.1 PIT Module Control Register (PIT_MCR)....................575 32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................577 32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................577 32.3.4 Timer Load Value Register (PIT_LDVALn)....................578 32.3.5 Current Timer Value Register (PIT_CVALn).....................578 32.3.6 Timer Control Register (PIT_TCTRLn)......................579 32.3.7...
Page 24 Section number Title Page 33.4 Functional description..............................593 33.4.1 LPTMR power and reset..........................593 33.4.2 LPTMR clocking............................593 33.4.3 LPTMR prescaler/glitch filter........................593 33.4.4 LPTMR compare............................595 33.4.5 LPTMR counter............................595 33.4.6 LPTMR hardware trigger..........................596 33.4.7 LPTMR interrupt............................596 Chapter 34 Real Time Clock (RTC) 34.1 Introduction...................................597 34.1.1 Features................................597 34.1.2...
Page 25 Section number Title Page 34.3.6 Register lock..............................609 34.3.7 Interrupt................................609 Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 35.1 Introduction...................................611 35.1.1 USB................................611 35.1.2 USB On-The-Go............................612 35.1.3 USB-FS Features............................613 35.2 Functional description..............................613 35.2.1 Data Structures.............................613 35.3 Programmers interface..............................614 35.3.1 Buffer Descriptor Table..........................614 35.3.2 RX vs.
Page 26 Section number Title Page 35.4.13 Status register (USBx_STAT)........................633 35.4.14 Control register (USBx_CTL)........................634 35.4.15 Address register (USBx_ADDR).........................635 35.4.16 BDT Page Register 1 (USBx_BDTPAGE1)....................636 35.4.17 Frame Number Register Low (USBx_FRMNUML)...................636 35.4.18 Frame Number Register High (USBx_FRMNUMH)..................637 35.4.19 Token register (USBx_TOKEN)........................637 35.4.20 SOF Threshold Register (USBx_SOFTHLD)....................638 35.4.21 BDT Page Register 2 (USBx_BDTPAGE2)....................639 35.4.22...
Page 27 Section number Title Page Chapter 37 Serial Peripheral Interface (SPI) 37.1 Introduction...................................655 37.1.1 Features................................655 37.1.2 Modes of Operation.............................656 37.1.3 Block Diagrams............................657 37.2 External Signal Description............................659 37.2.1 SPSCK — SPI Serial Clock.........................659 37.2.2 MOSI — Master Data Out, Slave Data In....................660 37.2.3 MISO —...
Page 28 Section number Title Page 37.4.11 Interrupts..............................681 37.5 Initialization/Application Information..........................683 37.5.1 Initialization Sequence..........................683 37.5.2 Pseudo-Code Example..........................684 Chapter 38 Inter-Integrated Circuit (I2C) 38.1 Introduction...................................687 38.1.1 Features................................687 38.1.2 Modes of operation............................688 38.1.3 Block diagram..............................688 38.2 I2C signal descriptions..............................689 38.3 Memory map and register descriptions.........................689 38.3.1 I2C Address Register 1 (I2Cx_A1)......................690 38.3.2...
Page 29 Section number Title Page 38.4.4 System management bus specification......................709 38.4.5 Resets................................712 38.4.6 Interrupts..............................712 38.4.7 Programmable input glitch filter........................714 38.4.8 Address matching wakeup...........................715 38.4.9 DMA support...............................715 38.5 Initialization/application information...........................716 Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) 39.1 Introduction...................................721 39.1.1 Features................................721 39.1.2 Modes of operation............................722 39.1.3 Block diagram..............................722 39.2...
Page 30 Section number Title Page 39.3.2 Transmitter functional description.......................738 39.3.3 Receiver functional description........................740 39.3.4 Additional UART functions.........................743 39.3.5 Interrupts and status flags..........................745 Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) 40.1 Introduction...................................747 40.1.1 Features................................747 40.1.2 Modes of operation............................747 40.1.3 Block diagram..............................748 40.2 Register definition.................................750 40.2.1...
Page 31 Section number Title Page 40.3.6 Additional UART functions.........................769 Chapter 41 General-Purpose Input/Output (GPIO) 41.1 Introduction...................................771 41.1.1 Features................................771 41.1.2 Modes of operation............................771 41.1.3 GPIO signal descriptions..........................772 41.2 Memory map and register definition..........................773 41.2.1 Port Data Output Register (GPIOx_PDOR)....................775 41.2.2 Port Set Output Register (GPIOx_PSOR)....................776 41.2.3 Port Clear Output Register (GPIOx_PCOR)....................776 41.2.4...
Page 32 Section number Title Page 42.1.2 Modes of operation............................785 42.1.3 Block diagram..............................786 42.2 External signal description............................787 42.2.1 TSI[15:0]..............................787 42.3 Register definition.................................787 42.3.1 TSI General Control and Status Register (TSIx_GENCS)................787 42.3.2 TSI DATA Register (TSIx_DATA)......................792 42.3.3 TSI Threshold Register (TSIx_TSHD)......................793 42.4 Functional description..............................793 42.4.1 Capacitance measurement..........................794 42.4.2...
Page 33: About This Document
Chapter 1 About This Document Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale KL25 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the KL25 microcontroller in a system. Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:...
Page 34: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 35: Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis L series of ARM® Cortex™-M0+ MCUs and KL25 product family. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 Kinetis L Series The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal ARM Cortex-M0+ MCUs in the industry.
Page 36 Kinetis L Series Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and human- machine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the entry-point to the Kinetis L series and is pin compatible with the 8-bit S08PT family.
Page 37 Chapter 2 Introduction • Optimized access to program memory: Accesses on alternate cycles reduces power consumption • 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex- M3/M4: Reuse existing compilers and debug tools • Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory •...
Page 38: Kl25 Sub-Family Introduction
KL25 Sub-Family Introduction • Connectivity and Communications: • Up to three UARTs, all UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes.
Page 39: Module Functional Categories
Chapter 2 Introduction 2.4 Module functional categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ® ARM Cortex-M0+ core •...
Page 40: System Modules
Module functional categories 2.4.1 ARM® Cortex™-M0+ Core Modules The following core modules are available on this device. Table 2-2. Core modules Module Description ARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments.
Page 41: Memories And Memory Interfaces
Chapter 2 Introduction Table 2-3. System modules (continued) Module Description Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources.
Page 42: Security And Integrity Modules
Module functional categories 2.4.5 Security and Integrity modules The following security and integrity modules are available on this device: Table 2-6. Security and integrity modules Module Description Watchdog Timer (WDOG) Watchdog Timer keeps a watch on the system functioning and resets it in case of its failure.
Page 43: Communication Interfaces
Chapter 2 Introduction Table 2-8. Timer modules Module Description Timer/PWM module (TPM) • Selectable TPM clock mode • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running counter or modulo counter with counting be up or up- down •...
Page 44: Human-Machine Interfaces
Orderable part numbers 2.4.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications.
Page 45: Chip Configuration
Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • Module block diagrams showing immediate connections within the device • Specific module-to-module interactions not necessarily discussed in the individual module chapters •...
Page 46: Kl25 Sub-Family Reference Manual, Rev. 3, September
Module to Module Interconnects Table 3-1. Module to Module Interconnects (continued) Peripheral Signal — to Peripheral Use Case Control Comment LPTMR Hardware trigger ADC (Trigger) ADC Triggering SOPT7_ADC0T — (A or B) RGSEL (4 bit field), ADC0PRETRG SEL to select A or B TPMx ADC (Trigger)
Page 47 Chapter 3 Chip Configuration Table 3-1. Module to Module Interconnects (continued) Peripheral Signal — to Peripheral Use Case Control Comment LPTMR Hardware trigger TPMx TPM Trigger TPMx_CONF[T — input RGSEL] (4 bit field) TPMx TPMx TPM Trigger TPMx_CONF[T — input RGSEL] (4 bit field) TPM1...
Page 48: Analog Reference Options
Core Modules 3.2.2 Analog reference options Several analog blocks have selectable reference voltages as shown in the below table. These options allow analog peripherals to share or have separate analog references. Care should be taken when selecting analog references to avoid cross talk noise. Table 3-2.
Page 49 Chapter 3 Chip Configuration Debug Interrupts ARM Cortex-M0+ Crossbar switch Core Figure 3-1. Core configuration Table 3-3. Reference links to related information Topic Related module Reference Full description ARM Cortex-M0+ core, ARM Cortex-M0+ Technical Reference Manual, r0p0 r0p0 System memory map System memory map Clocking Clock distribution...
Page 50 Core Modules Table 3-4. Table 3. ARM Cortex-M0+ parameter settings (continued) Parameter Verilog Name Value Description Endianess Little endian control for data transfers Breakpoints BKPT Implements 2 breakpoints Debug Support 1 = Present Halt Event Support HALTEV 1 = Present I/O Port 1 = Present Implements single-cycle ld/st...
Page 51: Nested Vectored Interrupt Controller (Nvic) Configuration
Chapter 3 Chip Configuration 3.3.1.3 System Tick Timer The CLKSOURCE bit in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
Page 52 Core Modules Table 3-5. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus ARM Cortex-M0+ core ARM Cortex-M0+ core (PPB) 3.3.2.1 Interrupt priority levels This device supports 4 priority levels for interrupts.
Page 53 Chapter 3 Chip Configuration Table 3-7. Interrupt vector assignments (continued) Address Vector NVIC Source module Source description register number 0x0000_0000 — — ARM core Initial Stack Pointer 0x0000_0004 — — ARM core Initial Program Counter 0x0000_0008 — — ARM core Non-maskable Interrupt (NMI) 0x0000_000C —...
Page 54 Core Modules Table 3-7. Interrupt vector assignments (continued) Address Vector NVIC Source module Source description register number 0x0000_0090 Alarm interrupt 0x0000_0094 Seconds interrupt 0x0000_0098 Single interrupt vector for all channels 0x0000_009C — — 0x0000_00A0 USB OTG 0x0000_00A4 DAC0 0x0000_00A8 TSI0 0x0000_00AC 0x0000_00B0 LPTMR0...
Page 55: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Chapter 3 Chip Configuration • NVICIPR2[23:22] 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Clock logic Wake-up requests...
Page 56: System Modules
System Modules Table 3-10. AWIC stop wake-up sources (continued) Wake-up source Description CMP0 Interrupt in normal or trigger mode Address match wakeup UART0 Any interrupt provided clock remains enabled UART1 and UART2 Active edge on RXD Alarm or seconds interrupt Any interrupt NMI pin TPMx...
Page 57: System Mode Controller (Smc) Configuration
Chapter 3 Chip Configuration 3.4.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access System Mode Resets Controller (SMC) Figure 3-5.
Page 58: Low-Leakage Wake-Up Unit (Llwu) Configuration
System Modules Peripheral bridge Register access Module Module signals signals Power Management Controller (PMC) Figure 3-6. PMC configuration Table 3-13. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Full description System Mode System Mode Controller...
Page 59 Chapter 3 Chip Configuration Peripheral bridge 0 Register access Wake-up requests Low-Leakage Wake-up Module Unit (LLWU) Module Figure 3-7. Low-Leakage Wake-up Unit configuration Table 3-14. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Clocking Clock distribution...
Page 60: Mcm Configuration
System Modules Table 3-15. Wakeup Sources LLWU pin Module source or pin name LLWU_P5 PTB0 LLWU_P6 PTC1 LLWU_P7 PTC3 LLWU_P8 PTC4 LLWU_P9 PTC5 LLWU_P10 PTC6 LLWU_P14 PTD4 LLWU_P15 PTD6 LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI0 LLWU_M5IF RTC Alarm LLWU_M6IF Reserved...
Page 61: Crossbar-Light Switch Configuration
Chapter 3 Chip Configuration Table 3-16. Reference links to related information (continued) Topic Related module Reference Transfer Flash memory Flash memory controller controller 3.4.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 62: Peripheral Bridge Configuration
System Modules Table 3-17. Reference links to related information (continued) Topic Related module Reference Crossbar switch slave Peripheral bridge Peripheral bridge 2-ported peripheral GPIO controller GPIO controleer 3.4.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core unified bus...
Page 63: Dma Request Multiplexer Configuration
Chapter 3 Chip Configuration Transfers Transfers AIPS-Lite peripheral bridge Figure 3-10. Peripheral bridge configuration Table 3-18. Reference links to related information Topic Related module Reference Full description Peripheral bridge Peripheral bridge (AIPS-Lite) (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch...
Page 64 System Modules Peripheral bridge 0 Register access Requests Module Channel request DMA Request Module Multiplexer Module Figure 3-11. DMA request multiplexer configuration Table 3-19. Reference links to related information Topic Related module Reference Full description DMA request DMA Mux multiplexer System memory map System memory map Clocking...
Page 65 Chapter 3 Chip Configuration Table 3-20. DMA request sources - MUX 0 (continued) Source Source module Source description Async DMA number capable Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — SPI0 Receive SPI0 Transmit SPI1...
Page 66: Dma Controller Configuration
System Modules Table 3-20. DMA request sources - MUX 0 (continued) Source Source module Source description Async DMA number capable Reserved — Reserved — Port control module Port A Reserved — Reserved — Port control module Port D Reserved — TPM0 Overflow TPM1...
Page 67: Computer Operating Properly (Cop) Watchdog Configuration
Chapter 3 Chip Configuration Peripheral bridge 0 Register access Transfers Requests DMA Controller Figure 3-12. DMA Controller configuration Table 3-21. Reference links to related information Topic Related module Reference Full description DMA controller DMA controller System memory map System memory map Clocking Clock distribution Power management...
Page 68 System Modules Table 3-22. Reference links to related information (continued) Topic Related module Reference Programming model System Integration Module (SIM) 3.4.10.1 COP clocks The two clock inputs for the COP are the 1 kHz clock and the bus clock. 3.4.10.2 COP watchdog operation The COP watchdog is intended to force a system reset when the application software fails to execute as expected.
Page 69 Chapter 3 Chip Configuration Table 3-23. COP configuration options (continued) Control Bits Clock Source COP Window Opens COP Overflow Count COPCTRL[COPCLKS] COPCTRL[COPT] (COPCTRL[COPW]=1) 1 kHz cycles (256 ms) 1 kHz cycles (1024 ms) 6,144 cycles cycles 49,152 cycles cycles 196,608 cycles cycles After the bus clock source is selected, windowed COP operation is available by setting COPCTRL[COPW] in the SIM.
Page 70: Clock Modules
Clock Modules 3.4.10.3 Clock Gating This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the SIM module. Clock Modules 3.5.1 MCG Configuration This section summarizes how the module has been configured in the chip.
Page 71: Osc Configuration
Chapter 3 Chip Configuration 3.5.2 OSC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Module signals System oscillator Figure 3-15.
Page 72: Memories And Memory Interfaces
Memories and Memory Interfaces Memories and Memory Interfaces 3.6.1 Flash Memory Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Register access Transfers...
Page 73 Chapter 3 Chip Configuration Table 3-27. KL25 flash memory size (continued) Device Program flash (KB) Block 0 (P-Flash) address range MKL25Z128VFM4 0x0000_0000 – 0x0001_FFFF MKL25Z32VFT4 0x0000_0000 – 0x0000_7FFF MKL25Z64VFT4 0x0000_0000 – 0x0000_FFFF MKL25Z128VFT4 0x0000_0000 – 0x0001_FFFF MKL25Z32VLH4 0x0000_0000 – 0x0000_7FFF MKL25Z64VLH4 0x0000_0000 –...
Page 74: Flash Memory Controller Configuration
Memories and Memory Interfaces 3.6.1.4 Flash Modes The flash memory chapter defines two modes of operation - NVM normal and NVM special modes. On this device, The flash memory only operates in NVM normal mode. All references to NVM special mode should be ignored. 3.6.1.5 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory via the SW-DP debug port by setting MDM-AP CONTROL[0].
Page 75: Sram Configuration
Chapter 3 Chip Configuration Transfers Transfers Flash memory controller Figure 3-18. Flash memory controller configuration Table 3-28. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory controller controller System memory map System memory map Clocking Clock Distribution Transfers...
Page 76 Memories and Memory Interfaces 3.6.3.1 SRAM Sizes This device contains SRAM which could be accessed by bus masters through the cross- bar switch. The amount of SRAM for the devices covered in this document is shown in the following table. Table 3-30.
Page 77: Analog
Chapter 3 Chip Configuration 0x2000_0000 – SRAM_size/4 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size(3/4) - 1 Figure 3-20. SRAM blocks memory map For example, for a device containing 16 KB of SRAM the ranges are: • SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF •...
Page 78 Analog Peripheral bus controller 0 Register access Module signals 16-bit SAR ADC Other peripherals Figure 3-21. 16-bit SAR ADC configuration Table 3-31. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC 16-bit SAR ADC System memory map System memory map Clocking Clock distribution...
Page 79 Chapter 3 Chip Configuration Table 3-32. Number of KL25 ADC channels (continued) Device Number of ADC channels MKL25Z64VLK4 MKL25Z128VLK4 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate.
Page 80 Analog ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 01011 AD11 Reserved ADC0_SE11 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved Reserved 10010 AD18...
Page 81: Cmp Configuration
Chapter 3 Chip Configuration 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals Other peripherals Figure 3-22.
Page 82 Analog The CMP does not support window compare function and CMP_CR1[WE] must always be written to 0. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0).
Page 83: 12-Bit Dac Configuration
Chapter 3 Chip Configuration is provided from the LPTMR. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration.
Page 84: Timers
Timers 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or selected as an input to the analog comparator or ADC. 3.7.3.3 12-bit DAC Analog Supply and Reference Connections This device includes dedicated VDDA and VSSA pins. This device contains separate VREFH and VREFL pins on 48-pin and higher devices.
Page 85 Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Module signals Other peripherals Figure 3-24. TPM configuration Table 3-36. Reference links to related information Topic Related module Reference Full description Timer/PWM Module Timer/PWM Module System memory map System memory map Clocking Clock distribution Power management...
Page 86 Timers 3.8.1.2 Clock Options The TPM blocks are clocked from a single TPM clock that can be selected from OSCERCLK, MCGIRCLK, MCGPLLCLK/2, or MCGFLLCLK. The selected source is controlled by SIM_SOPT2[TPMSRC] and SIM_SOPT2[PLLFLLSEL]control registers. Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the counter increments after a synchronized (to the selected TPM clock source) rising edge detect of an external clock input.
Page 87: Pit Configuration
Chapter 3 Chip Configuration 3.8.1.4 Global Timebase Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit. TPM1 is configured as the global time when this option is enabled. 3.8.1.5 TPM Interrupts The TPM has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller.
Page 88: Low-Power Timer Configuration
Timers Table 3-40. PIT channel assignments for periodic DMA triggering PIT Channel DMA Channel Number PIT Channel 0 DMA Channel 0 PIT Channel 1 DMA Channel 1 3.8.2.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module.
Page 89 Chapter 3 Chip Configuration Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.3.1 LPTMR Instantiation Information The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator.
Page 90: Rtc Configuration
Timers NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock Chip clock number MCGIRCLK — internal reference clock (not available in LLS and VLLS modes) LPO — 1 kHz clock (not available in VLLS0 mode) ERCLK32K (not available in VLLS0 mode when using 32 kHz oscillator)
Page 91: Communication Interfaces
Chapter 3 Chip Configuration 3.8.4.1 RTC Instantiation Information RTC prescaler is clocked by ERCLK32K. RTC is reset on POR Only. RTC_CR[OSCE] can override the configuration of the System OSC, configuring the OSC for 32kHz crystal operation in all power modes (except VLLS0) and through any System Reset.
Page 92 Communication interfaces USB controller USB voltage FS/LS regulator transceiver VREGIN VOUT33 Figure 3-28. USB Subsystem Overview 3.9.1.1 USB Wakeup When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action.
Page 93 Chapter 3 Chip Configuration 2 AA Cells To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP USB0_DM Controller XCVR Figure 3-29. USB regulator AA cell usecase 3.9.1.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD.
Page 94 Communication interfaces To PMC and Pads VOUT33 stab Chip TYPE A VREGIN VBUS Si2301 Charger Regulator USB0_DP Controller XCVR USB0_DM Li-Ion Figure 3-30. USB regulator Li-ion usecase 3.9.1.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD.
Page 95 Chapter 3 Chip Configuration 3.9.1.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals Transfers USB controller Figure 3-32.
Page 96: Spi Configuration
Communication interfaces Module signals USB Voltage Regulator Figure 3-33. USB Voltage Regulator configuration Table 3-44. Reference links to related information Topic Related module Reference Full description USB Voltage Regulator USB Voltage Regulator System memory map System memory map Clocking Clock Distribution USB controller USB controller Signal Multiplexing...
Page 97: I2C Configuration
Chapter 3 Chip Configuration Table 3-45. Reference links to related information (continued) Topic Related module Reference Signal Multiplexing Port control Signal Multiplexing 3.9.2.1 SPI Instantiation Information This device contains two SPI module that supports 8-bit data length. SPI0 is clocked on the bus clock. SPI1 is clocked from the system clock. SPI1 is therefore disabled in "Partial Stop Mode".
Page 98: Uart Configuration
Communication interfaces 3.9.3.1 IIC Instantiation Information This device has two IIC module. When the package pins associated with IIC have their mux select configured for IIC operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration. The digital glitch filter implemented in the IICx module, controlled by the I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts.
Page 99: Human-Machine Interfaces (Hmi)
Chapter 3 Chip Configuration 3.9.4.1 UART0 overview The UART0 module supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate. This module supports LIN slave operation. The module can remain functional in VLPS mode provided the clock it is using remains enabled.
Page 100 Human-machine interfaces (HMI) Table 3-48. Reference links to related information (continued) Topic Related module Reference Power management Power management Crossbar switch Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 GPIO Instantiation Information The device includes four pins, PTB0, PTB1, PTD6, and PTD7, with high current drive capability.
Page 101: Tsi Configuration
Chapter 3 Chip Configuration Table 3-49. Ports Summary (continued) Feature Port A Port B Port C Port D Port E Slew Rate Enable PTA3/PTA14/ PTB10/PTB11/ PTC3/PTC4/PTC5/ PTD4/PTD5/PTD6/ PTE16/PTE17/ at reset PTA15/PTA16/ PTB16/PTB17 = PTC6/ PTD7=Disabled; PTE18/ PTA17=Disabled; Disabled; PTC7=Disabled; Others=Enabled PTE19=Disabled;...
Page 102: Memory Map
Human-machine interfaces (HMI) Peripheral bridge Register access Module signals Touch sense input module Figure 3-38. TSI configuration Table 3-50. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control...
Page 103 Chapter 3 Chip Configuration Table 3-51. Number of KL25 TSI channels (continued) Device TSI channels MKL25Z128VLH4 MKL25Z32VLK4 MKL25Z64VLK4 MKL25Z128VLK4 3.10.2.2 TSI Interrupts The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source.
Page 104 Human-machine interfaces (HMI) KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 105: Introduction
Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
Page 106: Flash Memory Map
Flash Memory Map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core 0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core 0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core 0xF000_4000–0xF7FF_FFFF Reserved –...
Page 107: Alternate Non-Volatile Irc User Trim Description
Chapter 4 Memory Map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers.
Page 108: Peripheral Bridge (Aips-Lite) Memory Map
Peripheral bridge (AIPS-Lite) memory map 4.6 Peripheral bridge (AIPS-Lite) memory map The peripheral memory map is accessible via one slave port on the crossbar in the 0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that defines a 1024 KB address space. The three regions associated with this space are: •...
Page 109: Peripheral Bridge (Aips-Lite) Memory Map
Chapter 4 Memory Map 4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — 0x4000_3000 — 0x4000_4000 — 0x4000_5000 — 0x4000_6000 — 0x4000_7000 — 0x4000_8000 DMA controller 0x4000_9000...
Page 110: Kl25 Sub-Family Reference Manual, Rev. 3, September
Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 — 0x4002_A000 — 0x4002_B000 — 0x4002_C000 — 0x4002_D000 —...
Page 111 Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4004_A000 Port B multiplexing control 0x4004_B000 Port C multiplexing control 0x4004_C000 Port D multiplexing control 0x4004_D000 Port E multiplexing control 0x4004_E000 —...
Page 112: Modules Restricted Access In User Mode
Private Peripheral Bus (PPB) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4007_1000 — 0x4007_2000 USB OTG FS/LS 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 — 0x4007_5000 — 0x4007_6000 SPI 0 0x4007_7000...
Page 113 Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_E000–0xE000_EFFF System Control Space 0xE000_E000–0xE000_E00F Reserved (SCS) 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC 0xE000_ED00–0xE000_ED8F System Control Block 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved 0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF...
Page 114 Private Peripheral Bus (PPB) memory map KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 115: Introduction
Chapter 5 Clock Distribution 5.1 Introduction This chapter presents the clock architecture for the device, the overview of the clocks and includes a terminology section. The Cortex M0+ resides within a synchronous core platform, where the processor and bus masters, Flash and peripherals clocks can be configured independently. The clock distribution figure shows how clocks from the MCG and XOSC modules are distributed to the microcontroller’s other function units.
Page 116: Clock Definitions
Clock definitions 4 MHz IRC FCRDIV Clock options for MCGIRCLK some peripherals 32 kHz IRC (see note) Core clock, OUTDIV1 platform clock, and system clock MCGOUTCLK Bus clock/ OUTDIV4 Flash clock MCGFLLCLK FRDIV MCGPLLCLK MCGPLLCLK/ ÷2 MCGFLLCLK System oscillator EXTAL0 OSCCLK XTAL_CLK OSCERCLK...
Page 117: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description Flash clock Flash memory clock. On this device it is the same as Bus clock. MCGIRCLK MCG output of the slow or fast internal reference clock MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or MCG's external reference clock that sources the core, system, bus, and flash clock.
Page 118 Clock definitions Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock In all stop modes divider System clock Up to 48 MHz Up to 4 MHz...
Page 119: Internal Clocking Requirements
Chapter 5 Clock Distribution Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency UART0 clock Up to 48 MHz Up to 4 MHz MCGIRCLK, SIM_SOPT2[UART0SR MCGPLLCLK/2, C]=00 or selected clock MCGFLLCLK, or source disabled.
Page 120: Vlpr Mode Clocking
Internal clocking requirements FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Description 0x7 (divide by 8) 0x1 (divide by 2) Low power boot 0x3 (divide by 4) 0x1 (divide by 2) Low power boot 0x1 (divide by 2) 0x1 (divide by 2) Low power boot 0x0 (divide by 1) 0x1 (divide by 2)
Page 121: Clock Gating
Chapter 5 Clock Distribution 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock.
Page 122: Pmc 1-Khz Lpo Clock
Module clocks Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Bus clock OSCERCLK — Bus clock — — Bus clock — — Timers Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 Bus clock — — LPTMR Bus clock LPO, OSCERCLK, —...
Page 123: Rtc Clocking
Chapter 5 Clock Distribution COP clock Bus clock SIM_COPCTRL[COPCLKS] Figure 5-2. COP clock generation 5.7.3 RTC clocking The RTC module can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the RTC is to continue operating in all required low-power modes.
Page 124: Tpm Clocking
Module clocks MCGIRCLK LPTMRx prescaler/glitch ERCLK32K filter clock RTC_CLKIN OSCERCLK OSC32KCLK SIM_SOPT1[OSC32KSEL] LPTMRx_PSR[PCS] Figure 5-4. LPTMRx prescaler/glitch filter clock generation 5.7.5 TPM clocking The counter for the TPM modules have a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the TPMx is to continue operating in all required low-power modes.
Page 125: Uart Clocking
Chapter 5 Clock Distribution NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. USB_CLKIN USB 48MHz MCGFLLCLK ÷2 MCGPLLCLK...
Page 126 Module clocks KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 127: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •...
Page 128: Power-On Reset (Por)
Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V ).
Page 129 Chapter 6 Reset and Boot 6.2.2.1.1 Reset pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the reset control (RCM) register set control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR.
Page 130 Reset 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system reset.
Page 131: Mcu Resets
Chapter 6 Reset and Boot 6.2.2.7 Stop mode acknowledge error (SACKERR) This reset is generated if the core attempts to enter stop mode or Compute Operation, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. A module might not acknowledge the entry to stop mode if an error condition occurs.
Page 132 Reset 6.2.3.1 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and RTC. The POR Only reset also causes all other reset types to occur. 6.2.3.2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM.
Page 133: Reset Pin
Chapter 6 Reset and Boot 6.2.3.6 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash...
Page 134: Boot
Boot • DWT • NVIC • Crossbar bus switch • AHB-AP • Private peripheral bus 6.3 Boot This section describes the boot sequence, including sources and options. Some configuration information such as clock trim values stored in factory programmed flash locations is autoloaded. 6.3.1 Boot sources The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table.
Page 135: Boot Sequence
Chapter 6 Reset and Boot The MCU uses the FTFA_FOPT register bits to configure the device at reset as shown in the following table. Table 6-2. Flash Option Register (FTFA_FOPT) Bit Definitions Field Value Definition Reserved Reserved for future expansion. FAST_INIT Select initialization speed on POR, VLLSx, and any system reset .
Page 136 Boot 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control reset to disabled).
Page 137: Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking Modes This sections describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering STOP mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL).
Page 138: Dma Wakeup
Clocking Modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on- chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
Page 139: Compute Operation
Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wakeup can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag.
Page 140: Peripheral Doze
Clocking Modes During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral space remains accessible during Compute Operation, including the MCM, NVIC, IOPORT and SysTick. Although access to the GPIO registers via the IOPORT is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules.
Page 141: Clock Gating
Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence.
Page 142 Power modes The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1.
Page 143: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLLS1 (Very Most peripherals are disabled (with clocks stopped), but OSC, LLWU, Sleep Deep Wakeup Reset Low Leakage LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used Stop1) to wake up.
Page 144 Module Operation in Low Power Modes (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 4 MHz and 1 Mbps) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: •...
Page 145 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx 4 MHz IRC 4 MHz IRC static - static - static - no clock MCGIRCLK MCGIRCLK output optional; PLL optional optional Core clock 4 MHz max Platform clock...
Page 146 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx SPI1 master mode 2 master mode 2 static, slave static, slave static Mbps, Mbps, mode receive mode receive slave mode 1 slave mode 1 Mbps Mbps...
Page 147 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx Async Async Async Async Async operation operation operation operation operation Async operation in CPO FF in PSTOP2 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled.
Page 148 Module Operation in Low Power Modes KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 149: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits.
Page 150: Security Interactions With Debug
Security Interactions with other Modules 8.3.1 Security Interactions with Debug When flash security is active the SWD port cannot access the memory resources of the MCU. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit to trigger a mass erase (Erase All Blocks) command.
Page 151: Debug
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM CoreSight architecture and is configured to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints.
Page 152: Swd Status And Control Registers
SWD status and control registers 9.3 SWD status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure.
Page 153: Mdm-Ap Control Register
Chapter 9 Debug DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SW-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) APSEL Data[31:0] A[7:4] A[3:2] RnW Decode SELECT[31:24] (APSEL) selects the AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP...
Page 154: Mdm-Ap Status Register
SWD status and control registers Table 9-3. MDM-AP Control register assignments (continued) Name Secure Description Debug Request Set to force the core to halt. If the core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state.
Page 155 Chapter 9 Debug 9.3.2 MDM-AP Status Register Table 9-4. MDM-AP Status register assignments Name Description Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register.
Page 156: Kl25 Sub-Family Reference Manual, Rev. 3, September
Debug Resets Table 9-4. MDM-AP Status register assignments (continued) Name Description LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS.
Page 157: Micro Trace Buffer (Mtb)
Chapter 9 Debug 9.5 Micro Trace Buffer (MTB) The Micro Trace Buffer (MTB) provides a simple execution trace capability for the Cortex-M0+ processor. When enabled, the MTB records changes in program flow reported by the Cortex-M0+ processor, via the execution trace interface, into a configurable region of the SRAM.
Page 158 Debug & Security KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 159: Introduction
Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.
Page 160: Port Control And Interrupt Module Features
Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Port control and interrupt module features • 32-pin ports NOTE Not all pins are available on the device. See the following section for details.
Page 161: Clock Gating
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-2. Port control register configuration summary (continued) This field Generally Except for Resets to Configurability resets to PORTx_PC No exceptions - all are cleared on reset. — Only implemented for ports that support interrupt and DMA functionality.
Page 162 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP — — — PTE2 DISABLED PTE2 SPI1_SCK — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI — — — PTE4 DISABLED PTE4 SPI1_PCS0 — — — PTE5 DISABLED PTE5 —...
Page 163 Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_CLKIN0 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_CLKIN1 LPTMR0_ ALT1 RESET_b RESET_b PTA20 PTB0/ ADC0_SE8/ ADC0_SE8/ PTB0/ I2C0_SCL TPM1_CH0...
Page 164: Kl25 Pinouts
Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP — — — PTC16 DISABLED PTC16 — — — PTC17 DISABLED PTC17 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 — PTD2 DISABLED PTD2...
Page 165 Chapter 10 Signal Multiplexing and Signal Descriptions PTE0 PTE1 PTE2 PTC3/LLWU_P7 PTE3 PTC2 PTE4 PTC1/LLWU_P6/RTC_CLKIN PTE5 PTC0 PTB19 PTB18 USB0_DP PTB17 USB0_DM PTB16 PTB11 VOUT33 VREGIN PTB10 PTE20 PTB9 PTE21 PTB8 PTE22 PTB3 PTE23 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19...
Page 166 Pinout PTE0 PTE1 PTC3/LLWU_P7 PTC2 USB0_DP PTC1/LLWU_P6/RTC_CLKIN USB0_DM PTC0 VOUT33 PTB19 VREGIN PTB18 PTE20 PTB17 PTE21 PTB16 PTE22 PTB3 PTE23 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-3. KL25 64-pin LQFP pinout diagram KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 167 Chapter 10 Signal Multiplexing and Signal Descriptions PTC3/LLWU_P7 PTC2 USB0_DP PTC1/LLWU_P6/RTC_CLKIN USB0_DM PTC0 VOUT33 PTB17 VREGIN PTB16 PTE20 PTB3 PTE21 PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 10-4. KL25 48-pin QFN pinout diagram KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 168: Module Signal Description Tables
Module Signal Description Tables PTC3/LLWU_P7 PTE0 PTC2 PTC1/LLWU_P6/RTC_CLKIN USB0_DP USB0_DM PTB1 VOUT33 PTB0/LLWU_P5 VREGIN RESET_b VDDA PTA19 VSSA PTA18 Figure 10-5. KL25 32-pin QFN pinout diagram 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter.
Page 169: Core Modules
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.1 Core Modules Table 10-3. SWD Signal Descriptions Chip signal name Module signal Description name SWD_DIO SWD_DIO Serial wire debug data input/output. The SWD_DIO pin is used by Input / an external debug tool for communication and device control. This Output pin is pulled up internally.
Page 170: Analog
Module Signal Description Tables 10.4.5 Analog Table 10-6. ADC 0 Signal Descriptions Chip signal name Module signal Description name ADC0_DPn DADP3–DADP0 Differential Analog Channel Inputs ADC0_DMn DADM3–DADM0 Differential Analog Channel Inputs ADC0_SEn Single-Ended Analog Channel Inputs VREFH Voltage Reference Select High REFSH VREFL Voltage Reference Select Low...
Page 171: Communication Interfaces
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-10. TPM 1 Signal Descriptions (continued) Chip signal name Module signal Description name TPM1_CH[1:0] TPM_CHn TPM channel (n = 5 to 0) Table 10-11. TPM 2 Signal Descriptions Chip signal name Module signal Description name TPM_CLKIN[2:0]...
Page 172 Module Signal Description Tables Table 10-16. SPI0 Signal Descriptions Chip signal name Module signal Description name SPI0_MISO MISO Master Data In, Slave Data Out SPI0_MOSI MOSI Master Data Out, Slave Data In SPI0_SCLK SPSCK SPI Serial Clock SPI0_PCS0 Slave Select Table 10-17.
Page 173: Human-Machine Interfaces (Hmi)
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-21. UART 1 Signal Descriptions Chip signal name Module signal Description name UART1_TX Transmit data UART1_RX Receive data Table 10-22. UART 2 Signal Descriptions Chip signal name Module signal Description name UART2_TX Transmit data UART2_RX Receive data...
Page 174 Module Signal Description Tables KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 175: Introduction
Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 11.2 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
Page 176: Modes Of Operation
External signal description • Individual pull control fields with pullup, pulldown, and pull-disablesupport on selected pins • Individual drive strength field supporting high and low drive strength on selected pins • Individual slew rate field supporting fast and slow slew rates on selected pins •...
Page 177: Detailed Signal Description
Chapter 11 Port control and interrupts (PORT) Table 11-1. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2.
Page 178 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_9020 Pin Control Register n (PORTA_PCR8) See section 11.5.1/183 4004_9024 Pin Control Register n (PORTA_PCR9) See section 11.5.1/183 4004_9028 Pin Control Register n (PORTA_PCR10) See section...
Page 179 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A020 Pin Control Register n (PORTB_PCR8) See section 11.5.1/183 4004_A024 Pin Control Register n (PORTB_PCR9) See section 11.5.1/183 4004_A028 Pin Control Register n (PORTB_PCR10)
Page 180 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B020 Pin Control Register n (PORTC_PCR8) See section 11.5.1/183 4004_B024 Pin Control Register n (PORTC_PCR9) See section 11.5.1/183 4004_B028 Pin Control Register n (PORTC_PCR10) See section...
Page 181 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C020 Pin Control Register n (PORTD_PCR8) See section 11.5.1/183 4004_C024 Pin Control Register n (PORTD_PCR9) See section 11.5.1/183 4004_C028 Pin Control Register n (PORTD_PCR10) See section...
Page 182 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D020 Pin Control Register n (PORTE_PCR8) See section 11.5.1/183 4004_D024 Pin Control Register n (PORTE_PCR9) See section 11.5.1/183 4004_D028 Pin Control Register n (PORTE_PCR10) See section 11.5.1/183...
Page 183: Pin Control Register N (Portx_Pcrn)
Chapter 11 Port control and interrupts (PORT) 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE Refer to the Signal Multiplexing and Signal Descriptions chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin.
Page 184 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–16 Interrupt Configuration IRQC This field is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes.
Page 185: Global Pin Control Low Register (Portx_Gpclr)
Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Passive input filter is disabled on the corresponding pin. Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
Page 186: Global Pin Control High Register (Portx_Gpchr)
Memory map and register definition PORTx_GPCLR field descriptions (continued) Field Description Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. 15–0 Global Pin Write Data GPWD Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
Page 187: Functional Description
Chapter 11 Port control and interrupts (PORT) PORTx_ISFR field descriptions Field Description 31–0 Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. Configured interrupt is not detected. Configured interrupt is detected.
Page 188: Global Pin Control
Functional description 11.6.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function.
Page 189 Chapter 11 Port control and interrupts (PORT) During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the Low-Power mode. KL25 Sub-Family Reference Manual, Rev.
Page 190 Functional description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 191: System Integration Module (Sim)
Chapter 12 System integration module (SIM) 12.1 Introduction The system integration module (SIM) provides system control and chip configuration registers. 12.1.1 Features • System clocking configuration • System clock divide values • Architectural clock gating control • ERCLK32K clock selection •...
Page 192 Memory map and register definition NOTE The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute Width...
Page 193: System Options Register 1 (Sim_Sopt1)
Chapter 12 System integration module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h OSC32KSEL Reset Reserved Reset * Notes: • Reserved field: Device specific value. SIM_SOPT1 field descriptions Field Description...
Page 194: Sopt1 Configuration Register (Sim_Sopt1Cfg)
Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 19–18 32K oscillator clock select OSC32KSEL Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This bit is reset only on POR/LVD. System oscillator (OSC32KCLK) Reserved RTC_CLKIN LPO 1kHz 17–6 This field is reserved.
Page 195: System Options Register 2 (Sim_Sopt2)
Chapter 12 System integration module (SIM) SIM_SOPT1CFG field descriptions (continued) Field Description SOPT1 USBSSTB cannot be written. SOPT1 USBSSTB can be written. USB voltage regulator VLP standby write enable UVSWE Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. This register bit clears after a write to USBVSTBY.
Page 196 Memory map and register definition SIM_SOPT2 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 27–26 UART0 clock source select UART0SRC Selects the clock source for the UART0 transmit and receive clock. Clock disabled MCGFLLCLK clock or MCGPLLCLK/2 clock OSCERCLK clock...
Page 197: System Options Register 4 (Sim_Sopt4)
Chapter 12 System integration module (SIM) SIM_SOPT2 field descriptions (continued) Field Description Selects either the RTC 1 Hz clock or the OSC clock to be output on the RTC_CLKOUT pin. RTC 1 Hz clock is output on the RTC_CLKOUT pin. OSCERCLK clock is output on the RTC_CLKOUT pin.
Page 198 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description TPM1 external clock driven by TPM_CLKIN0 pin. TPM1 external clock driven by TPM_CLKIN1 pin. TPM0 External Clock Pin Select TPM0CLKSEL Selects the external pin used to drive the clock to the TPM0 module. NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module.
Page 199: System Options Register 5 (Sim_Sopt5)
Chapter 12 System integration module (SIM) 12.2.5 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset Reset SIM_SOPT5 field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 200: System Options Register 7 (Sim_Sopt7)
Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description UART1_TX pin UART1_TX pin modulated with TPM1 channel 0 output UART1_TX pin modulated with TPM2 channel 0 output Reserved This field is reserved. Reserved This read-only field is reserved and always has the value 0. UART0 receive data source select UART0RXSRC Selects the source for the UART0 receive data.
Page 201 Chapter 12 System integration module (SIM) SIM_SOPT7 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0. Alternate trigger selected for ADC0.
Page 202: System Device Identification Register (Sim_Sdid)
Memory map and register definition 12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h FAMID SUBFAMID SERIESID SRAMSIZE REVID DIEID PINID Reset * Notes: • FAMID field: Device specific value. • SUBFAMID field: Device specific value. •...
Page 203 Chapter 12 System integration module (SIM) SIM_SDID field descriptions (continued) Field Description 0110 32 KB 0111 64 KB 15–12 Device revision number REVID Specifies the silicon implementation number for the device. 11–7 Device die number DIEID Specifies the silicon implementation number for the device. 6–4 This field is reserved.
Page 204: System Clock Gating Control Register 4 (Sim_Scgc4)
Memory map and register definition 12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h SPI1 SPI0 Reset I2C1 I2C0 Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 1. 27–24 This field is reserved.
Page 205 Chapter 12 System integration module (SIM) SIM_SCGC4 field descriptions (continued) Field Description Clock disabled Clock enabled 17–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. UART2 Clock Gate Control UART2 This bit controls the clock gate to the UART2 module.
Page 206: System Clock Gating Control Register 5 (Sim_Scgc5)
Memory map and register definition 12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Reset Reset SIM_SCGC5 field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 207: System Clock Gating Control Register 6 (Sim_Scgc6)
Chapter 12 System integration module (SIM) SIM_SCGC5 field descriptions (continued) Field Description Clock disabled Clock enabled Port A Clock Gate Control PORTA This bit controls the clock gate to the Port A module. Clock disabled Clock enabled 8–7 This field is reserved. Reserved This read-only field is reserved and always has the value 1.
Page 208 Memory map and register definition SIM_SCGC6 field descriptions Field Description DAC0 Clock Gate Control DAC0 This bit controls the clock gate to the DAC0 module. Clock disabled Clock enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. RTC Access Control This bit controls software access and interrupts to the RTC module.
Page 209: System Clock Gating Control Register 7 (Sim_Scgc7)
Chapter 12 System integration module (SIM) SIM_SCGC6 field descriptions (continued) Field Description 14–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DMA Mux Clock Gate Control DMAMUX This bit controls the clock gate to the DMA Mux module. Clock disabled Clock enabled Flash Memory Clock Gate Control...
Page 210: System Clock Divider Register 1 (Sim_Clkdiv1)
Memory map and register definition 12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. NOTE Reset value loaded during System Reset from FTF_FOPT[LPBOOT]. Address: 4004_7000h base + 1044h offset = 4004_8044h OUTDIV1 OUTDIV4 Reset...
Page 211: Flash Configuration Register 1 (Sim_Fcfg1)
Chapter 12 System integration module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 18–16 Clock 4 output divider value OUTDIV4 This field sets the divide value for the bus and flash clock and is in addition to the System clock divide ratio.
Page 212 Memory map and register definition SIM_FCFG1 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 27–24 Program flash size PFSIZE This field specifies the amount of program flash memory available on the device . Undefined values are reserved.
Page 213: Flash Configuration Register 2 (Sim_Fcfg2)
Chapter 12 System integration module (SIM) 12.2.14 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 Reset Reset * Notes: • MAXADDR0 field: Device specific value indicating amount of implemented flash. SIM_FCFG2 field descriptions Field Description This field is reserved.
Page 214: Unique Identification Register Mid Low (Sim_Uidml)
Memory map and register definition SIM_UIDMH field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Unique Identification Unique identification for the device. 12.2.16 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Reset * Notes:...
Page 215: Cop Control Register (Sim_Copc)
Chapter 12 System integration module (SIM) 12.2.18 COP Control Register (SIM_COPC) All of the bits in this register can be written only once after a reset. Address: 4004_7000h base + 1100h offset = 4004_8100h Reset COPT Reset SIM_COPC field descriptions Field Description 31–4...
Page 216: Service Cop Register (Sim_Srvcop)
Functional description 12.2.19 Service COP Register (SIM_SRVCOP) Address: 4004_7000h base + 1104h offset = 4004_8104h Reserved SRVCOP Reset SIM_SRVCOP field descriptions Field Description 31–8 This field is reserved. Reserved 7–0 Sevice COP Register SRVCOP Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter. 12.3 Functional description Introduction section.
Page 217: System Mode Controller (Smc)
Chapter 13 System Mode Controller (SMC) 13.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
Page 218 Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways.
Page 219: Memory Map And Register Descriptions
Chapter 13 System Mode Controller (SMC) Table 13-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic.
Page 220 Memory map and register descriptions The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode.
Page 221: Power Mode Control Register (Smc_Pmctrl)
Chapter 13 System Mode Controller (SMC) 13.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS.
Page 222: Stop Control Register (Smc_Stopctrl)
Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field Description 2–0 Stop Mode Control STOPM When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register.
Page 223: Power Mode Status Register (Smc_Pmstat)
Chapter 13 System Mode Controller (SMC) SMC_STOPCTRL field descriptions (continued) Field Description clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated. STOP - Normal Stop mode PSTOP1 - Partial Stop with both system and bus clocks disabled PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option...
Page 224: Functional Description
Functional description Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS PMSTAT NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS 000_0001...
Page 225 Chapter 13 System Mode Controller (SMC) Any RESET VLPW VLPR WAIT STOP VLPS VLLS 3, 2, 1, 0 Figure 13-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-7. Power mode transition triggers Transition # From Trigger conditions...
Page 226 Functional description Table 13-7. Power mode transition triggers (continued) Transition # From Trigger conditions STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR The core, system, bus and flash clock frequencies are restricted in this mode.
Page 227: Power Mode Entry/Exit Sequencing
Chapter 13 System Mode Controller (SMC) Table 13-7. Power mode transition triggers (continued) Transition # From Trigger conditions PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin. VLPR PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is...
Page 228 Functional description Reset Control Low - Module Leakage (RCM) Wakeup (LLWU) Stop/Wait LP exit LP exit System Bus masters low power bus (non-CPU) Clock Mode CCM low power bus Control Bus slaves low power bus Controller Module (SMC) (CCM) PMC low power bus Flash low power bus MCG enable System...
Page 229: Run Modes
Chapter 13 System Mode Controller (SMC) 13.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1.
Page 230 Functional description 13.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 •...
Page 231: Wait Modes
Chapter 13 System Mode Controller (SMC) To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
Page 232: Stop Modes
Functional description When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 13.4.5 Stop modes This device contains a variety of stop modes to meet your application needs.
Page 233 Chapter 13 System Mode Controller (SMC) A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
Page 234 Functional description Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt.
Page 235: Debug In Low Power Modes
Chapter 13 System Mode Controller (SMC) When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set.
Page 236 Functional description The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin.
Page 237: Power Management Controller (Pmc)
Chapter 14 Power Management Controller (PMC) 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 14.2 Features The PMC features include: •...
Page 238: Lvd Reset Operation
Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point;...
Page 239: I/O Retention
Chapter 14 Power Management Controller (PMC) 14.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode.
Page 240: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
Memory map and register descriptions 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Page 241: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chapter 14 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field Description Low-Voltage Detect Reset Enable LVDRE This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 3–2 This field is reserved.
Page 242: Regulator Status And Control Register (Pmc_Regsc)
Memory map and register descriptions PMC_LVDSC2 field descriptions Field Description Low-Voltage Warning Flag LVWF This read-only status bit indicates a low-voltage warning event. LVWF is set when V transitions below Supply the trip point, or after reset and V is already below V .
Page 243 Chapter 14 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Read ACKISO REGONS Reserved BGEN Reserved BGBE Write Reset PMC_REGSC field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 244 Memory map and register descriptions KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 245: Low-Leakage Wakeup Unit (Llwu)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes.
Page 246: Modes Of Operation
Introduction 15.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wakeup events until the user has acknowledged the wakeup via a write to the PMC_REGSC[ACKISO] bit.
Page 247: Block Diagram
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive.
Page 248: Llwu Signal Descriptions
LLWU signal descriptions 15.2 LLWU signal descriptions The signal properties of LLWU are shown in the following table. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 15-1. LLWU signal descriptions Signal Description LLWU_Pn...
Page 249: Llwu Pin Enable 1 Register (Llwu_Pe1)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 15.3.1/249 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 15.3.2/250 4007_C002 LLWU Pin Enable 3 register (LLWU_PE3) 15.3.3/251 4007_C003 LLWU Pin Enable 4 register (LLWU_PE4) 15.3.4/252...
Page 250: Llwu Pin Enable 2 Register (Llwu_Pe2)
Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P1 WUPE1...
Page 251: Llwu Pin Enable 3 Register (Llwu_Pe3)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P6 WUPE6 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 252: Llwu Pin Enable 4 Register (Llwu_Pe4)
Memory map/register definition LLWU_PE3 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P11 WUPE11 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4...
Page 253: Llwu Module Enable Register (Llwu_Me)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) Address: 4007_C000h base + 3h offset = 4007_C003h Read WUPE15 WUPE14 WUPE13 WUPE12 Write Reset LLWU_PE4 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P15 WUPE15 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 254 Memory map/register definition types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 Write Reset LLWU_ME field descriptions Field Description Wakeup Module Enable For Module 7...
Page 255: Llwu Flag 1 Register (Llwu_F1)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions (continued) Field Description Wakeup Module Enable For Module 0 WUME0 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source 15.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode.
Page 256 Memory map/register definition LLWU_F1 field descriptions (continued) Field Description LLWU_P6 input was not a wakeup source LLWU_P6 input was a wakeup source Wakeup Flag For LLWU_P5 WUF5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF5.
Page 257: Llwu Flag 2 Register (Llwu_F2)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.3.7 LLWU Flag 2 register (LLWU_F2) LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
Page 258: Llwu Flag 3 Register (Llwu_F3)
Memory map/register definition LLWU_F2 field descriptions (continued) Field Description Wakeup Flag For LLWU_P12 WUF12 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF12. LLWU_P12 input was not a wakeup source LLWU_P12 input was a wakeup source Wakeup Flag For LLWU_P11 WUF11...
Page 259 Chapter 15 Low-Leakage Wakeup Unit (LLWU) NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
Page 260: Llwu Pin Filter 1 Register (Llwu_Filt1)
Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 2 input was not a wakeup source Module 2 input was a wakeup source Wakeup flag For module 1 MWUF1...
Page 261: Llwu Pin Filter 2 Register (Llwu_Filt2)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT1 field descriptions (continued) Field Description Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 262: Functional Description
Functional description LLWU_FILT2 field descriptions (continued) Field Description Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 263: Lls Mode
Chapter 15 Low-Leakage Wakeup Unit (LLWU) For internal module wakeup operation, the WUMEx bit enables the associated module as a wakeup source. 15.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution. 15.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage...
Page 264: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 265: Reset Control Module (Rcm)
Chapter 16 Reset Control Module (RCM) 16.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 16.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control.
Page 266 Reset memory map and register descriptions NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x82 • LVD (without POR) — 0x02 • VLLS mode wakeup due to RESET pin assertion — 0x41 •...
Page 267: System Reset Status Register 1 (Rcm_Srs1)
Chapter 16 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor.
Page 268: Reset Pin Filter Control Register (Rcm_Rpfc)
Reset memory map and register descriptions RCM_SRS1 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Stop Mode Acknowledge Error Reset SACKERR Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more...
Page 269: Reset Pin Filter Width Register (Rcm_Rpfw)
Chapter 16 Reset Control Module (RCM) Address: 4007_F000h base + 4h offset = 4007_F004h Read RSTFLTSS RSTFLTSRW Write Reset RCM_RPFC field descriptions Field Description 7–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reset Pin Filter Select in Stop Mode RSTFLTSS Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS...
Page 270 Reset memory map and register descriptions RCM_RPFW field descriptions (continued) Field Description 00000 Bus clock filter count is 1 00001 Bus clock filter count is 2 00010 Bus clock filter count is 3 00011 Bus clock filter count is 4 00100 Bus clock filter count is 5 00101...
Page 271: Bit Manipulation Engine (Bme)
Chapter 17 Bit Manipulation Engine (BME) 17.1 Introduction The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify- write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. This architectural capability is also known as "decorated storage" as it defines a mechanism for providing additional semantics for load and store operations to memory-mapped peripherals beyond just the reading and writing of data values to the addressed memory locations.
Page 272: Overview
Introduction 17.1.1 Overview The following figure is a generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers. Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST IO Port MTB Port AHB Bus PRAM Array RGPIO AXBS...
Page 273: Modes Of Operation
Chapter 17 Bit Manipulation Engine (BME) • Resides between a crossbar switch slave port and a peripheral bridge bus controller • 2-stage pipeline design matching the AHB system bus protocol • Combinationally passes non-decorated accesses to peripheral bridge bus controller •...
Page 274: Memory Map And Register Definition
Memory Map and Register Definition 17.3 Memory Map and Register Definition The BME module provides a memory-mapped capability and does not include any programming model registers. The exact set of functions supported by the BME are detailed in the Functional Description.
Page 275 Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER hclk BME AHB Input Bus next 5..v_wxyz mx_haddr next mx_hattr next mx_hwrite wdata mx_hwdata mx_hrdata mx_hready BME AHB Output Bus next 400v_wxyz 400v_wxyz sx_haddr next sx_hattr next sx_hwrite wdata bfi rdata sx_hwdata rdata sx_hrdata sx_hready...
Page 276 Functional Description NOTE Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. 17.4.1.1 Decorated Store Logical AND (AND) This command performs an atomic read-modify-write of the referenced memory location.
Page 277 Chapter 17 Bit Manipulation Engine (BME) Table 17-1. Cycle definitions of decorated store: logical AND Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 278 Functional Description Table 17-2. Cycle definitions of decorated store: logical OR Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 279 Chapter 17 Bit Manipulation Engine (BME) Table 17-3. Cycle definitions of decorated store: logical XOR Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 280: Bme Decorated Loads
Functional Description & ~mask // modify wdata & mask mem[accessAddress & 0xE007FFFF, size] = tmp // memory write The write data operand (wdata) associated with the store instruction contains the bit field to be inserted. It must be properly aligned within a right-justified container, that is, within the lower 8 bits for a byte operation, the lower 16 bits for a halfword or the entire 32 bits for a word operation.
Page 281 Chapter 17 Bit Manipulation Engine (BME) 17.4.2 BME Decorated Loads The functions supported by the BME's decorated loads include two single-bit load-and- {set, clear} operators plus unsigned bit field extracts. For the two load-and-{set, clear} operations, BME converts a single decorated AHB load transaction into a 2-cycle atomic read-modify-write sequence, where the combined read-modify operations are performed in the first AHB data phase, and then the write is performed in the second AHB data phase as the original read data is returned to the processor core.
Page 282 Functional Description • Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register • Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual) memory address is output •...
Page 283 Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER hclk BME AHB Input Bus 5..v_wxyz next mx_haddr next mx_hattr next mx_hwrite mx_hwdata ubfx mx_hrdata mx_hready BME AHB Output Bus 400v_wxyz next sx_haddr next sx_hattr next sx_hwrite sx_hwdata rdata sx_hrdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 5..v_wxyz...
Page 284 Functional Description 17.4.2.1 Decorated Load Load-and-Clear 1 Bit (LAC1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and zeroes the bit in the memory space after performing an atomic read-modify-write sequence. The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core.
Page 285 Chapter 17 Bit Manipulation Engine (BME) 17.4.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and sets the bit in the memory space after performing an atomic read-modify-write sequence.
Page 286 Functional Description 17.4.2.3 Decorated Load Unsigned Bit Field Extract (UBFX) This command extracts a bit field defined by LSB position (b) and the bit field width (w +1) from the memory "container" defined by the access size associated with the load instruction using a 2-cycle read sequence.
Page 287: Additional Details On Decorated Addresses And Gpio Accesses
Chapter 17 Bit Manipulation Engine (BME) Table 17-7. Cycle definitions of decorated load: unsigned bit field extract Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Idle AHB address phase <next> Decode decoration; Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Logically right shift registered bit mask;...
Page 288: Application Information
Application Information Table 17-8. Decorated peripheral and GPIO address details (continued) Peripheral address space Description 0x4400_0000 - 0x4FFF_FFFF Decorated AND, OR, XOR, LAC1, LAS1 references to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 - 0x5FFF_FFFF Decorated BFI, UBFX references to peripherals and GPIO only based at 0x4000_F000 17.5 Application Information In this section, GNU assembler macros with C expression operands are presented as examples of the required instructions to perform decorated operations.
Page 289 Chapter 17 Bit Manipulation Engine (BME) :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORW(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "str r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORH(ADDR,WDATA) __asm("ldr r3, =(3<<26);"...
Page 290 Application Information KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 291: Miscellaneous Control Module (Mcm)
Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 18.1.1 Features The MCM includes the following features: •...
Page 292: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory map/register descriptions MCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar Switch (AXBS) Master Configuration F000_300A 000Dh 18.2.2/293 (MCM_PLAMC) F000_300C Platform Control Register (MCM_PLACR) 0000_0000h 18.2.3/293 F000_3040 Compute Operation Control Register (MCM_CPO) 0000_0000h 18.2.4/296 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
Page 293: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
Chapter 18 Miscellaneous Control Module (MCM) 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: F000_3000h base + Ah offset = F000_300Ah Read Write Reset MCM_PLAMC field descriptions...
Page 294: Kl25 Sub-Family Reference Manual, Rev. 3, September
Memory map/register descriptions The cache in flash controller is enabled and caching both instruction and data type fetches after reset. It is possible to have these states for the cache: DFCC DFCIC DFCDA Description Cache is on for both instruction and data. Cache is on for instruction and off for data.
Page 295 Chapter 18 Miscellaneous Control Module (MCM) MCM_PLACR field descriptions (continued) Field Description Disable Flash Controller Speculation DFCS This field is used to disable flash controller speculation. Enable flash controller speculation. Disable flash controller speculation. Enable Flash Data Speculation EFDS This field is used to enable flash data speculation. Disable flash data speculation.
Page 296: Compute Operation Control Register (Mcm_Cpo)
Memory map/register descriptions 18.2.4 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: F000_3000h base + 40h offset = F000_3040h Reset Reset MCM_CPO field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compute Operation wakeup on interrupt CPOWOI No effect.
Page 297 Chapter 18 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 298 Memory map/register descriptions KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 299: Micro Trace Buffer (Mtb)
Chapter 19 Micro Trace Buffer (MTB) 19.1 Introduction Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight Micro Trace Buffer to provide program trace capabilities. The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-M0+ Processor; in this document, it is simply abbreviated as the MTB.
Page 300 Introduction Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST IO Port AHB Bus MTB Port PRAM Array RGPIO Slave Peripherals Alt-Master PBRIDGE DMA_4ch AXBS Array Figure 19-1. Generic Cortex-M0+ core platform block diagram As shown in the block diagram, the platform RAM (PRAM) controller connects to two input buses: •...
Page 301 Chapter 19 Micro Trace Buffer (MTB) The following figure shows how the execution trace information is stored in memory as a sequence of packets. Nth destination address Odd word address Nth source address Even word address Incrementing SRAM memory address Start bit 2nd destination address 2nd source address...
Page 302: Features
Introduction • Destination address field set to bits[31:1] of the EXC_RETURN value. See the ARM v6-M Architecture Reference Manual. • The A-bit set to 0. • The second packet has the: • Source address field set to bits[31:1] of the EXC_RETURN value. •...
Page 303: Modes Of Operation
Chapter 19 Micro Trace Buffer (MTB) • Two DWT comparators (addresses or address + data) provide programmable start/ stop recording • CoreSight compliant debug functionality 19.1.3 Modes of Operation The MTB_RAM and MTB_DWT functions do not support any special modes of operation.
Page 304: Memory Map And Register Definition
Memory Map and Register Definition In addition, there are two signals formed by the MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can be configured using the trace watchpoints to define programmable addresses and data values to affect the program trace recording state.
Page 305 Chapter 19 Micro Trace Buffer (MTB) MTB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_0FB4 Lock Status Register (MTB_LOCKSTAT) 0000_0000h 19.31.9/312 19.31.10/ F000_0FB8 Authentication Status Register (MTB_AUTHSTAT) 0000_0000h 19.31.11/ F000_0FBC Device Architecture Register (MTB_DEVICEARCH) 4770_0A31h 19.31.12/ F000_0FC8 Device Configuration Register (MTB_DEVICECFG)
Page 306 Memory Map and Register Definition 19.31.1 MTB Position Register (MTB_POSITION) The MTB_POSITION register is the trace write address pointer and wrap bit. This register can be modified by the explicit programming model writes. It is also automatically updated by the MTB hardware when trace packets are being recorded. Address: F000_0000h base + 0h offset = F000_0000h POINTER Reset...
Page 307 Chapter 19 Micro Trace Buffer (MTB) 19.31.2 MTB Master Register (MTB_MASTER) The MTB_MASTER register contains the main program trace enable plus other trace controls. This register can be modified by the explicit programming model writes. MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically updated by the MTB hardware.
Page 308 Memory Map and Register Definition MTB_MASTER field descriptions (continued) Field Description NOTE: If the EN bit is set to 0 because the MTB_FLOW[WATERMARK] field is set, then it is not automatically set to 1 if the TSTARTEN bit is 1 and the TSTART input is HIGH. In this case, tracing can only be restarted if the MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by software.
Page 309 Chapter 19 Micro Trace Buffer (MTB) 19.31.3 MTB Flow Register (MTB_FLOW) The MTB_FLOW register contains the watermark address and the autostop/autohalt control bits. Address: F000_0000h base + 8h offset = F000_0008h WATERMARK Reset WATERMARK Reset * Notes: • x = Undefined at reset. MTB_FLOW field descriptions Field Description...
Page 310 Memory Map and Register Definition 19.31.4 MTB Base Register (MTB_BASE) The read-only MTB_BASE Register indicates where the RAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB RAM location, by a debug agent and is defined by a hardware design parameter. For these devices, the base address is defined by the expression: MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4) Address: F000_0000h base + Ch offset = F000_000Ch...
Page 311 Chapter 19 Micro Trace Buffer (MTB) 19.31.6 Claim TAG Set Register (MTB_TAGSET) The Claim Tag Set Register returns the number of bits that can be set on a read, and enables individual bits to be set on a write. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Page 312 Memory Map and Register Definition 19.31.8 Lock Access Register (MTB_LOCKACCESS) The Lock Access Register enables a write access to component registers. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FB0h offset = F000_0FB0h LOCKACCESS Reset MTB_LOCKACCESS field descriptions...
Page 313 Chapter 19 Micro Trace Buffer (MTB) 19.31.10 Authentication Status Register (MTB_AUTHSTAT) The Authentication Status Register reports the required security level and current status of the security enable bit pairs. Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent.
Page 314 Memory Map and Register Definition 19.31.11 Device Architecture Register (MTB_DEVICEARCH) This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset MTB_DEVICEARCH field descriptions...
Page 315 Chapter 19 Micro Trace Buffer (MTB) 19.31.13 Device Type Identifier Register (MTB_DEVICETYPID) This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTB_DEVICETYPID field descriptions...
Page 316: Mtb_Dwt Memory Map
Memory Map and Register Definition 19.31.15 Component ID Register (MTB_COMPIDn) These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3d COMPID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 317 Chapter 19 Micro Trace Buffer (MTB) MTBDWT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_1FCC Device Type Identifier Register (MTBDWT_DEVICETYPID) 0000_0004h 19.32.8/325 F000_1FD0 Peripheral ID Register (MTBDWT_PERIPHID4) See section 19.32.9/326 F000_1FD4 Peripheral ID Register (MTBDWT_PERIPHID5) See section 19.32.9/326 F000_1FD8 Peripheral ID Register (MTBDWT_PERIPHID6)
Page 318 Memory Map and Register Definition MTBDWT_CTRL field descriptions (continued) Field Description MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events...
Page 319 Chapter 19 Micro Trace Buffer (MTB) 19.32.3 MTB_DWT Comparator Mask Register (MTBDWT_MASKn) The MTBDWT_MASKn registers define the size of the ignore mask applied to the reference address for address range matching by comparator n. Note the format of this mask field is different than the MTB_MASTER[MASK]. Address: F000_1000h base + 24h offset + (16d ×...
Page 320 Memory Map and Register Definition 19.32.4 MTB_DWT Comparator Function Register 0 (MTBDWT_FCT0) The MTBDWT_FCTn registers control the operation of comparator n. Address: F000_1000h base + 28h offset = F000_1028h Reset DATAVADDR0 DATAVSIZE FUNCTION Reset MTBDWT_FCT0 field descriptions Field Description 31–25 This field is reserved.
Page 321 Chapter 19 Micro Trace Buffer (MTB) MTBDWT_FCT0 field descriptions (continued) Field Description No match. Match occurred. 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–12 Data Value Address 0 DATAVADDR0...
Page 322 Memory Map and Register Definition 19.32.5 MTB_DWT Comparator Function Register 1 (MTBDWT_FCT1) The MTBDWT_FCTn registers control the operation of comparator n. Since the MTB_DWT only supports data value comparisons on comparator 0, there are several fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8). Address: F000_1000h base + 38h offset = F000_1038h Reset FUNCTION...
Page 323 Chapter 19 Micro Trace Buffer (MTB) MTBDWT_FCT1 field descriptions (continued) Field Description No match. Match occurred. 23–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–0 Function FUNCTION Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero.
Page 324 Memory Map and Register Definition Reset MTBDWT_TBCTRL field descriptions Field Description 31–28 Number of Comparators NUMCOMP This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes two registers. 27–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Action based on Comparator 1 match ACOMP1 When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has...
Page 325 Chapter 19 Micro Trace Buffer (MTB) 19.32.7 Device Configuration Register (MTBDWT_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FC8h offset = F000_1FC8h DEVICECFG Reset MTBDWT_DEVICECFG field descriptions...
Page 326: System Rom Memory Map
Memory Map and Register Definition 19.32.9 Peripheral ID Register (MTBDWT_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 327 Chapter 19 Micro Trace Buffer (MTB) 19.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. For core configurations like that supported by Cortex-M0+, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure.
Page 328 Memory Map and Register Definition ROM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_2FDC Peripheral ID Register (ROM_PERIPHID7) See section 19.33.4/330 F000_2FE0 Peripheral ID Register (ROM_PERIPHID0) See section 19.33.4/330 F000_2FE4 Peripheral ID Register (ROM_PERIPHID1) See section 19.33.4/330 F000_2FE8 Peripheral ID Register (ROM_PERIPHID2)
Page 329 Chapter 19 Micro Trace Buffer (MTB) 19.33.2 End of Table Marker Register (ROM_TABLEMARK) This register indicates end of table marker. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + Ch offset = F000_200Ch MARK Reset ROM_TABLEMARK field descriptions...
Page 330 Memory Map and Register Definition 19.33.4 Peripheral ID Register (ROM_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 331: Crossbar Switch Lite (Axbs-Lite)
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
Page 332: Functional Description
Functional Description 20.3 Functional Description 20.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request.
Page 333: Arbitration
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.3.2 Arbitration The crossbar switch supports two arbitration algorithms: • Fixed priority • Round robin The selection of the global slave port arbitration is controlled by MCM_PLACR[ARB]. For fixed priority, set ARB to 0. For round robin, set ARB to 1. This arbitration setting applies to all slave ports.
Page 334: Initialization/Application Information
Initialization/application information Table 20-1. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true: At the next clock edge • The current master is not running a transfer. •...
Page 335: Peripheral Bridge (Aips-Lite)
Chapter 21 Peripheral Bridge (AIPS-Lite) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space.
Page 336: General Operation
Functional description 21.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: •...
Page 337: Direct Memory Access Multiplexer (Dmamux)
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 22.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 4 DMA channels. This process is illustrated in the following figure. KL25 Sub-Family Reference Manual, Rev.
Page 338: Features
Introduction DMA channel #0 DMAMUX Source #1 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 22-1. DMAMUX block diagram 22.1.2 Features The DMAMUX module provides these features: •...
Page 339: External Signal Description
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
Page 340: Functional Description
Functional description NOTE Setting multiple CHCFG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCFGn[ENBL] bit. Address: 4002_1000h base + 0h offset + (1d × i), where i=0d to 3d Read ENBL TRIG...
Page 341: Dma Channels With Periodic Triggering Capability
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) • Channels which implement the normal routing functionality plus periodic triggering capability • Channels which implement only the normal routing functionality 22.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention.
Page 342: Freescale Semiconductor, Inc
Functional description The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen.
Page 343: Dma Channels With No Triggering Capability
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on- chip memory.
Page 344: Initialization/Application Information
Initialization/application information By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will impose on the system.
Page 345: Freescale Semiconductor, Inc
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
Page 346: Freescale Semiconductor, Inc
Initialization/application information 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared.
Page 347: Freescale Semiconductor, Inc
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
Page 348: Freescale Semiconductor, Inc
Initialization/application information KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 349: Dma Controller Module
Chapter 23 DMA Controller Module 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and programming model. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
Page 350: Features
Introduction The following figure is a simplified block diagram of the 4-channel DMA controller. DREQ0 DREQ1 DREQ2 DREQ3 DACK0 DACK1 DACK2 DACK3 Channel 0 Channel 1 Channel 2 Channel 3 SAR0 SAR1 SAR2 SAR3 Slave Interrupts DAR0 DAR1 DAR2 DAR3 Peripheral Bus DSR0 DSR1...
Page 351: Dma Transfer Overview
Chapter 23 DMA Controller Module • Continuous-mode or cycle-steal transfers from software or peripheral initiation • Automatic hardware acknowledge/done indicator from each channel • Independent source and destination address registers • Optional modulo addressing and automatic updates of source and destination addresses •...
Page 352: Memory Map And Registers
Memory Map and Registers Control and Data Memory/ Peripheral Read Write Memory/ Peripheral Control and Data Figure 23-2. Dual-Address Transfer Any operation involving a DMA channel follows the same three steps: 1. Channel initialization—The transfer control descriptor, contained in the channel registers, is loaded with address pointers, a byte-transfer count, and control information using accesses from the slave peripheral bus.
Page 353: Source Address Register (Dma_Sarn)
Chapter 23 DMA Controller Module DMA memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_8100 Source Address Register (DMA_SAR0) 0000_0000h 23.3.1/353 4000_8104 Destination Address Register (DMA_DAR0) 0000_0000h 23.3.2/354 DMA Status Register / Byte Count Register 4000_8108 0000_0000h 23.3.3/355...
Page 354: Destination Address Register (Dma_Darn)
Memory Map and Registers DMA_SARn field descriptions Field Description 31–0 Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data. Restriction: Bits 31-20 of this register must be written with one of only four allowed values.
Page 355: Dma Status Register / Byte Count Register (Dma_Dsr_Bcrn)
Chapter 23 DMA Controller Module DMA_DARn field descriptions (continued) Field Description After being written with one of the allowed values, bits 31-20 read back as the written value. After being written with any other value, bits 31-20 read back as an indeterminate value. 23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn) DSR and BCR are two logical registers that occupy one 32-bit address.
Page 356: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DSR_BCRn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Configuration error Any of the following conditions causes a configuration error: • BCR, SAR, or DAR does not match the requested transfer size. •...
Page 357: Dma Control Register (Dma_Dcrn)
Chapter 23 DMA Controller Module DMA_DSR_BCRn field descriptions (continued) Field Description greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After being written with a value in this range, bits 23-20 of BCR read back as 1111b. 23.3.4 DMA Control Register (DMA_DCRn) Address: 4000_8000h base + 10Ch offset + (16d ×...
Page 358: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description Cycle steal DMA continuously makes read/write transfers until the BCR decrements to 0. Forces a single read/write transfer per request. Auto-align AA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers are optimized based on the address and size.
Page 359: Freescale Semiconductor, Inc
Chapter 23 DMA Controller Module DMA_DCRn field descriptions (continued) Field Description 16-bit Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) Start transfer START DMA inactive The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
Page 360: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description 1010 Circular buffer size is 8 KB 1011 Circular buffer size is 16 KB 1100 Circular buffer size is 32 KB 1101 Circular buffer size is 64 KB 1110 Circular buffer size is 128 KB 1111 Circular buffer size is 256 KB Disable request...
Page 361: Functional Description
Chapter 23 DMA Controller Module 23.4 Functional Description In the following discussion, the term DMA request implies that DCRn[START] is set, or DCRn[ERQ] is set and then followed by assertion of the properly selected DMA peripheral request. The START bit is cleared when the channel is activated. Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and DCRn[DSIZE] are consistent with the source and destination addresses.
Page 362: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional Description 23.4.2 Channel Initialization and Startup Before a data transfer starts, the channel's transfer control descriptor must be initialized with information describing configuration, request-generation method, and pointers to the data to be moved. 23.4.2.1 Channel Prioritization The four DMA channels are prioritized based on number, with channel 0 having highest priority and channel 3 having the lowest, that is, channel 0 >...
Page 363: Dual-Address Data Transfer Mode
Chapter 23 DMA Controller Module • SARn and DARn change after each data transfer depending on DCRn[SSIZE, DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment values can be 1, 2, or 4 for 8-bit, 16-bit, or 32-bit transfers, respectively. If the address register is programmed to remain unchanged, the register is not incremented after the data transfer.
Page 364: Advanced Data Transfer Controls: Auto-Alignment
Functional Description • Dual-address write—The DMA controller drives the DARn value onto the system address bus. When the appropriate number of write cycles complete (multiple writes if the source size is larger than the destination), DARn increments by the appropriate number of bytes if DCRn[DINC] is set.
Page 365: Termination
Chapter 23 DMA Controller Module 3. Read 4 bytes from 0x2000_0004, increment SARn, write 4 bytes. 4. Repeat 4-byte operations until SARn equals 0x2000_00F0. 5. Read byte from 0x2000_00F0, increment SARn, write byte. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.
Page 366: Freescale Semiconductor, Inc
Functional Description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 367: Introduction
Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL).
Page 368: Freescale Semiconductor, Inc
Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. •...
Page 369: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) • Reference dividers for the Fast Internal Reference Clock are provided • MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals •...
Page 370: Freescale Semiconductor, Inc
Introduction Crystal Oscillator External Reference Clock CLKS OSCINIT0 PLLCLKEN0 MCG Crystal Oscillator Enable Detect EREFS0 IREFS HGO0 PLLS ATMS RANGE0 STOP IREFSTEN Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM IRCS Internal CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock FCTRIM n=0-7 MCGOUTCLK...
Page 371: Modes Of Operation
Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition.
Page 372: Mcg Control 1 Register (Mcg_C1)
Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 —...
Page 373: Mcg Control 2 Register (Mcg_C2)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Read LOCRE0 RANGE0 HGO0 EREFS0 IRCS Write Reset MCG_C2 field descriptions Field Description Loss of Clock Reset Enable LOCRE0 Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock.
Page 374: Mcg Control 3 Register (Mcg_C3)
Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description Slow internal reference clock selected. Fast internal reference clock selected. 24.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Read SCTRIM Write Reset * Notes: • x = Undefined at reset.
Page 375: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C4 field descriptions Field Description DCO Maximum Frequency with 32.768 kHz Reference DMX32 The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums.
Page 376: Mcg Control 5 Register (Mcg_C5)
Memory Map/Register Definition 24.3.5 MCG Control 5 Register (MCG_C5) Address: 4006_4000h base + 4h offset = 4006_4004h Read PLLCLKEN0 PLLSTEN0 PRDIV0 Write Reset MCG_C5 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. PLL Clock Enable PLLCLKEN0 Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK.
Page 377: Mcg Control 6 Register (Mcg_C6)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description Table 24-7. PLL External Reference Divide Factor (continued) 00100 01100 10100 11100 Reserve 00101 01101 10101 11101 Reserve 00110 01110 10110 11110 Reserve 00111 01111 10111 11111 Reserve 24.3.6 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Read...
Page 378: Mcg Status Register (Mcg_S)
Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. External clock monitor is disabled for OSC0.
Page 379: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) MCG_S field descriptions (continued) Field Description PLL has not lost lock since LOLS 0 was last cleared. PLL has lost lock since LOLS 0 was last cleared. Lock Status LOCK0 This bit indicates whether the PLL has acquired lock. Lock detection is only enabled when the PLL is enabled (either through clock mode selection or PLLCLKEN0=1 setting).
Page 380: Mcg Status And Control Register (Mcg_Sc)
Memory Map/Register Definition MCG_S field descriptions (continued) Field Description Source of internal reference clock is the slow clock (32 kHz IRC). Source of internal reference clock is the fast clock (4 MHz IRC). 24.3.8 MCG Status and Control Register (MCG_SC) Address: 4006_4000h base + 8h offset = 4006_4008h Read ATMF...
Page 381: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description 3–1 Fast Clock Internal Reference Divider FCRDIV Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). Divide Factor is 1 Divide Factor is 2.
Page 382: Mcg Control 7 Register (Mcg_C7)
Memory Map/Register Definition MCG_ATCVL field descriptions Field Description 7–0 ATM Compare Value Low ATCVL Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Read Write Reset...
Page 383: Mcg Control 9 Register (Mcg_C9)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C8 field descriptions (continued) Field Description Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. Generate a reset request on a PLL loss of lock indication.
Page 384: Functional Description
Functional Description 24.4 Functional Description 24.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 24-18. The arrows indicate the permitted MCG mode transitions. Reset BLPE BLPI Returns to the state that was active before Entered from any state when the MCU entered Stop mode, unless a the MCU enters Stop mode...
Page 385: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 24.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 24-16. Table 24-18. MCG modes of operation Mode Description FLL Engaged Internal...
Page 386: Freescale Semiconductor, Inc
Functional Description Table 24-18. MCG modes of operation (continued) Mode Description FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 •...
Page 387: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Table 24-18. MCG modes of operation (continued) Mode Description Bypassed Low Power Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: External (BLPE) • C1[CLKS] bits are written to 10 •...
Page 388: Mcg Internal Reference Clocks
Functional Description The C1[CLKS] bits can also be changed at any time, but the actual switch to the newly selected clock is shown by the S[CLKST] bits. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1.
Page 389: External Reference Clock
Chapter 24 Multipurpose Clock Generator (MCG) affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode.
Page 390: Mcg Pll Clock
Functional Description 24.4.6 MCG PLL clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set.
Page 391: Initialization / Application Information
Chapter 24 Multipurpose Clock Generator (MCG) Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV •...
Page 392: Freescale Semiconductor, Inc
Initialization / Application information 2. Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source.
Page 393: Using A 32.768 Khz Reference
Chapter 24 Multipurpose Clock Generator (MCG) • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz.
Page 394: Mcg Mode Switching
Initialization / Application information 24.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range.
Page 395: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Table 24-19. MCGOUTCLK Frequency Calculation Options (continued) Clock Mode Note MCGOUTCLK FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast PEE (PLL engaged external)
Page 396: Freescale Semiconductor, Inc
Initialization / Application information • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator.
Page 397: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode.
Page 398: Freescale Semiconductor, Inc
Initialization / Application information START IN FEI MODE C6 = 0x40 C2 = 0x1C BLPE MODE ? (S[LP]=1) C1 = 0x90 C2 = 0x1C (S[LP]=0) CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? CHECK S[IREFST] = 0? CHECK S[LOCK] = 1? CHECK S[CLKST] = %10? C1 = 0x10...
Page 399: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.
Page 400: Freescale Semiconductor, Inc
Initialization / Application information • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source.
Page 401: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? CHECK S[CLKST] = %10 ? C1 = 0x54 ENTER CHECK BLPE MODE ? S[IREFST] = 0? C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 C2 = 0x02...
Page 402: Freescale Semiconductor, Inc
Initialization / Application information 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency.
Page 403: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK S[IREFST] = 0? C2 = 0x00...
Page 404: Freescale Semiconductor, Inc
Initialization / Application information KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 405: Oscillator (Osc)
Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.2 Features and Modes Key features of the module are: •...
Page 406: Block Diagram
Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode.
Page 407: External Crystal / Resonator Connections
Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
Page 408: External Clock Connections
External Clock Connections XTAL EXTAL Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. XTAL EXTAL Crystal or Resonator Figure 25-4.
Page 409: Memory Map/Register Definitions
Chapter 25 Oscillator (OSC) XTAL EXTAL Clock Input Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/...
Page 410: Functional Description
Functional Description OSCx_CR field descriptions (continued) Field Description External reference clock is inactive. External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
Page 411: Freescale Semiconductor, Inc
Chapter 25 Oscillator (OSC) Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable...
Page 412: Osc Module Modes
Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 413: Counter
Chapter 25 Oscillator (OSC) Table 25-7. Oscillator Modes Mode Frequency Range High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, refer to the chip's Power Management details.
Page 414: Reset
Reset 25.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings.
Page 415: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 26 Flash Memory Controller (FMC) 26.1 Introduction The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between bus masters and the 32-bit program flash memory. • a buffer and a cache that can accelerate program flash memory data transfers. 26.1.1 Overview The Flash Memory Controller manages the interface between bus masters and the 32-bit program flash memory.
Page 416: Modes Of Operation
Modes of operation • 32-bit prefetch speculation buffer for program flash accesses with controls for instruction/data access • 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen 32-bit entries with invalidation control 26.2 Modes of operation The FMC operates only when a bus master accesses the program flash memory.
Page 417: Freescale Semiconductor, Inc
Chapter 26 Flash Memory Controller (FMC) • Data speculation is disabled • Data caching is enabled Though the default configuration provides flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. For example, the user may adjust the controls to enable buffering per access type (data or instruction).
Page 418: Freescale Semiconductor, Inc
Functional description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 419: Introduction
Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources.
Page 420: Features
Introduction 27.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 27.1.1.1 Program Flash Memory Features • Sector size of 1 Kbyte •...
Page 421: Glossary
Chapter 27 Flash Memory Module (FTFA) Interrupt Program flash Status Register access registers Memory controller Control registers To MCU's flash controller Figure 27-1. Flash Block Diagram 27.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
Page 422: External Signal Description
External Signal Description NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used.
Page 423: Flash Configuration Field Description
Chapter 27 Flash Memory Module (FTFA) 27.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Size (Bytes) Field Description...
Page 424: Register Descriptions
Memory Map and Registers user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-Byte records using the Read Once and Program Once commands (see Read Once Command Program Once Command).
Page 425: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Flash Common Command Object Registers 4002_000D 27.33.5/430 (FTFA_FCCOBA) Flash Common Command Object Registers 4002_000E 27.33.5/430 (FTFA_FCCOB9) Flash Common Command Object Registers 4002_000F 27.33.5/430 (FTFA_FCCOB8)
Page 426: Freescale Semiconductor, Inc
Memory Map and Registers FTFA_FSTAT field descriptions (continued) Field Description Flash command in progress Flash command has completed Flash Read Collision Error Flag RDCOLERR The RDCOLERR error bit indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0).
Page 427: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Address: 4002_0000h base + 1h offset = 4002_0001h Read ERSAREQ CCIE RDCOLLIE ERSSUSP Write Reset FTFA_FCNFG field descriptions Field Description Command Complete Interrupt Enable CCIE The CCIE bit controls interrupt generation when a flash command completes. Command complete interrupt disabled Command complete interrupt enabled.
Page 428: Freescale Semiconductor, Inc
Memory Map and Registers 27.33.3 Flash Security Register (FTFA_FSEC) This read-only register holds all bits associated with the security of the MCU and flash memory module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory.
Page 429: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA_FSEC field descriptions (continued) Field Description Freescale factory access granted Freescale factory access denied Freescale factory access denied Freescale factory access granted 1–0 Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources.
Page 430: Freescale Semiconductor, Inc
Memory Map and Registers 27.33.5 Flash Common Command Object Registers (FTFA_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Address: 4002_0000h base + 4h offset + (1d ×...
Page 431: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] Data Byte 6 Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number.
Page 432: Functional Description
Functional Description Program flash protection register Flash Configuration Field offset address FPROT2 0x0009 FPROT3 0x0008 To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field.
Page 433: Flash Protection
Chapter 27 Flash Memory Module (FTFA) 27.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers that protect 32 regions of the program flash memory as shown in the following figure Program flash 0x0_0000...
Page 434: Flash Operation In Low-Power Modes
Functional Description Note Vector addresses and their relative interrupt priority are determined at the MCU level. Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported.
Page 435: Flash Reads And Ignored Writes
Chapter 27 Flash Memory Module (FTFA) 27.4.5 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block.
Page 436: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional Description 27.4.8.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 27-25. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed.
Page 437: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails.
Page 438: Freescale Semiconductor, Inc
Functional Description START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Protection Violation Clear the old errors FPVIOL Check Write 0x30 to FSTAT register Set? Write to the FCCOB registers to load the required command parameter.
Page 439: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FCMD Command Program flash Function 0x09 Erase Flash Sector × Erase all bytes in a program flash sector. 0x40 Read 1s All Blocks × Verify that the program flash block is erased then release MCU security.
Page 440: Margin Read Commands
Functional Description 27.4.9 Margin Read Commands The Read-1s commands (Read 1s All Blocks and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply non- standard read reference levels to the program flash array reads performed by these commands.
Page 441: Flash Command Description
Chapter 27 Flash Memory Module (FTFA) 27.4.10 Flash Command Description This section describes all flash commands that can be launched by a command write sequence. The flash memory module sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: •...
Page 442: Freescale Semiconductor, Inc
Functional Description Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 27-27 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT[MGSTAT0] bit is set.
Page 443: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 27-30, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the FSTAT[MGSTAT0] bit is set.
Page 444: Freescale Semiconductor, Inc
Functional Description Table 27-32. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x03 (RDRSRC) Flash address [23:16] Flash address [15:8] Flash address [7:0] Returned Values Read Data [31:24] Read Data [23:16] Read Data [15:8] Read Data [7:0] User-provided values Resource Select Code (see Table 27-33)
Page 445: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device.
Page 446: Freescale Semiconductor, Inc
Functional Description Table 27-36. Program Longword Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 27.4.10.5 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 27-37.
Page 447: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers. If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF.
Page 448: Freescale Semiconductor, Inc
Functional Description Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE? Request Suspend...
Page 449: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.10.6 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e.
Page 450: Freescale Semiconductor, Inc
Functional Description 27.4.10.7 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command.
Page 451: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Table 27-44. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x43 (PGMONCE) Program Once record index (0x00 - 0x0F) Not Used Not Used Program Once Byte 0 value Program Once Byte 1 value Program Once Byte 2 value Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module...
Page 452: Freescale Semiconductor, Inc
Functional Description Table 27-46. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, then verifies that all are erased. If the flash memory module verifies that all flash memories were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state.
Page 453: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.10.10 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by Mode). Execution of the Verify Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see...
Page 454: Security
Functional Description Table 27-49. Verify Backdoor Access Key Command Error Handling (continued) Error Condition Error Bit Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down FSTAT[ACCERR] reset 27.4.11 Security...
Page 455: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.11.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected.
Page 456: Reset Sequence
Functional Description module reverts back to the flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field.
Page 457: Introduction
Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device.
Page 458: Block Diagram
Introduction • Configurable sample time and conversion speed/power • Conversion complete/hardware average complete flag and interrupt • Input clock selectable from up to four sources • Operation in Low-Power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock •...
Page 459: Adc Signal Descriptions
Chapter 28 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion trigger SC1n ADHWTSn control A D T R G ADHWT (SC2, CFG1, CFG2) C o m p a re tru e Control Registers A D A C K E N Async Clock Gen Interrupt ADACK A D C K...
Page 460: Voltage Reference Select
ADC Signal Descriptions Table 28-1. ADC Signal Descriptions Signal Description DADP3–DADP0 Differential Analog Channel Inputs DADM3–DADM0 Differential Analog Channel Inputs Single-Ended Analog Channel Inputs Voltage Reference Select High REFSH Voltage Reference Select Low REFSL Analog Power Supply Analog Ground 28.2.1 Analog Power (V The ADC analog portion uses V as its power connection.
Page 461: Analog Channel Inputs (Adx)
Chapter 28 Analog-to-Digital Converter (ADC) In some packages, V is connected in the package to V and V to V . If REFH REFL externally available, the positive reference(s) may be connected to the same potential as or may be driven by an external source to a level between the minimum Ref Voltage High and the V potential.
Page 462: Adc Status And Control Registers 1 (Adcx_Sc1N)
Register definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_B020 Status and Control Register 2 (ADC0_SC2) 0000_0000h 28.3.6/470 4003_B024 Status and Control Register 3 (ADC0_SC3) 0000_0000h 28.3.7/472 4003_B028 ADC Offset Correction Register (ADC0_OFS) 0000_0004h 28.3.8/474 4003_B02C ADC Plus-Side Gain Register (ADC0_PG)
Page 463: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) trigger mode. See the chip configuration information about the number of SC1n registers specific to this device. The SC1n registers have identical fields, and are used in a "ping- pong" approach to control ADC operation. At any one point in time, only one of the SC1n registers is actively controlling ADC conversions.
Page 464: Freescale Semiconductor, Inc
Register definition ADCx_SC1n field descriptions (continued) Field Description This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare result is true.
Page 465: Adc Configuration Register 1 (Adcx_Cfg1)
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 01111 When DIFF=0, AD15 is selected as input;...
Page 466: Freescale Semiconductor, Inc
Register definition ADCx_CFG1 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Low-Power Configuration ADLPC Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. Normal power configuration.
Page 467: Adc Configuration Register 2 (Adcx_Cfg2)
Chapter 28 Analog-to-Digital Converter (ADC) 28.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Reset ADLSTS Reset...
Page 468: Adc Data Result Register (Adcx_Rn)
Register definition ADCx_CFG2 field descriptions (continued) Field Description Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks. Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 1–0 Long Sample Time Select ADLSTS...
Page 469: Compare Value Registers (Adcx_Cvn)
Chapter 28 Analog-to-Digital Converter (ADC) Table 28-43. Data result register description (continued) Conversion D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format mode 10-bit single- Unsigned right- ended justified 9-bit differential Sign-extended 2's complement 8-bit single- Unsigned right-...
Page 470: Status And Control Register 2 (Adcx_Sc2)
Register definition Address: 4003_B000h base + 18h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Compare Value.
Page 471: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Active ADACT Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted.
Page 472: Status And Control Register 3 (Adcx_Sc3)
Register definition ADCx_SC2 field descriptions (continued) Field Description Alternate reference pair, that is, V and V . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved...
Page 473: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC3 field descriptions (continued) Field Description Calibration Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the calibration sequence.
Page 474: Adc Offset Correction Register (Adcx_Ofs)
Register definition 28.3.8 ADC Offset Correction Register (ADCx_OFS) The ADC Offset Correction Register (OFS) contains the user-selected or calibration- generated offset error correction value. This register is a 2’s complement, left-justified, 16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn.
Page 475: Adc Minus-Side Gain Register (Adcx_Mg)
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_PG field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Plus-Side Gain 28.3.10 ADC Minus-Side Gain Register (ADCx_MG) The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side input in differential mode.
Page 476: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Register definition Address: 4003_B000h base + 34h offset = 4003_B034h CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLPD 28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description.
Page 477: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLP4 28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: 4003_B000h base + 40h offset = 4003_B040h CLP3 Reset...
Page 478: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Register definition 28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: 4003_B000h base + 48h offset = 4003_B048h CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 Calibration Value CLP1...
Page 479: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
Chapter 28 Analog-to-Digital Converter (ADC) 28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD) The Minus-Side General Calibration Value (CLMx) registers contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0].
Page 480: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Register definition 28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4) For more information, see CLMD register description. Address: 4003_B000h base + 5Ch offset = 4003_B05Ch CLM4 Reset ADCx_CLM4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLM4...
Page 481: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Chapter 28 Analog-to-Digital Converter (ADC) 28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2) For more information, see CLMD register description. Address: 4003_B000h base + 64h offset = 4003_B064h CLM2 Reset ADCx_CLM2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 482: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
Functional description 28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0) For more information, see CLMD register description. Address: 4003_B000h base + 6Ch offset = 4003_B06Ch CLM0 Reset ADCx_CLM0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLM0...
Page 483: Clock Select And Divide Control
Chapter 28 Analog-to-Digital Converter (ADC) The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations. NOTE For the chip specific modes of operation, see the power management information of this MCU.
Page 484: Voltage Reference Selection
Functional description 28.4.2 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (V and V ) used for conversions. Each pair contains a REFSH REFSL positive reference that must be between the minimum Ref Voltage High and V , and a ground reference that must be at the same potential as V .
Page 485: Conversion Control
Chapter 28 Analog-to-Digital Converter (ADC) When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received. For example: • ADHWTSA active selects RA register • ADHWTSn active selects Rn register The conversion complete flag associated with the ADHWTSn received, that is, SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1.
Page 486: Freescale Semiconductor, Inc
Functional description Note Selecting more than one ADHWTSn prior to a conversion completion will result in unknown results. To avoid this, select only one ADHWTSn prior to a conversion completion. • Following the transfer of the result to the data registers when continuous conversion is enabled, that is, when ADCO=1.
Page 487: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) • Writing to SC1A while it is actively controlling a conversion, aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s. Writing to any of the SC1B–SC1n registers while that specific SC1B–SC1n register is actively controlling a conversion aborts the current conversion.
Page 488: Freescale Semiconductor, Inc
Functional description ADC configuration Sample time (ADCK cycles) CFG1[ADLSMP] CFG2[ADLSTS] CFG2[ADHSC] First or Single Subsequent The total conversion time depends upon: • The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS] • The MCU bus frequency • The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF] •...
Page 489: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) The maximum total conversion time for all configurations is summarized in the equation below. See the following tables for the variables referenced in the equation. Figure 28-62. Conversion time equation Table 28-70. Single or first continuous time adder (SFCAdder) CFG1[AD CFG2[AD CFG1[ADICLK]...
Page 490: Freescale Semiconductor, Inc
Functional description Table 28-73. Long sample time adder (LSTAdder) Long sample time adder CFG1[ADLSMP] CFG2[ADLSTS] (LSTAdder) 0 ADCK cycles 20 ADCK cycles 12 ADCK cycles 6 ADCK cycles 2 ADCK cycles Table 28-74. High-speed conversion time adder (HSCAdder) CFG2[ADHSC] High-speed conversion time adder (HSCAdder) 0 ADCK cycles 2 ADCK cycles Note...
Page 491: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) Table 28-75. Typical conversion time (continued) Variable Time AverageNum 20 ADCK cycles LSTAdder HSCAdder The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting conversion time is 3.75 µs.
Page 492: Freescale Semiconductor, Inc
Functional description • 8-bit Single-Ended mode with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 20 MHz • Long sample time disabled • High-speed conversion enabled The conversion time for this conversion is calculated by using the Figure 28-62, and the information provided in...
Page 493: Automatic Compare Function
Chapter 28 Analog-to-Digital Converter (ADC) Note The hardware average function can perform conversions on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the hardware average is completed if SC1n[AIEN] was set. 28.4.5 Automatic compare function The compare function can be configured to check whether the result is less than or greater-than-or-equal-to a single compare value, or, if the result falls within or outside a...
Page 494: Calibration Function
Functional description If the condition selected evaluates true, SC1n[COCO] is set. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, SC1n[COCO] is not set and the conversion result data will not be transferred to the result register, Rn.
Page 495: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) To initiate calibration, the user sets SC3[CAL] and the calibration will automatically begin if the SC2[ADTRG] is 0. If SC2[ADTRG] is 1, SC3[CAL] will not get set and SC3[CALF] will be set. While calibration is active, no ADC register can be written and no stop mode may be entered, or the calibration routine will be aborted causing SC3[CAL] to clear and SC3[CALF] to set.
Page 496: User-Defined Offset Function
Functional description 28.4.7 User-defined offset function OFS contains the user-selected or calibration-generated offset error correction value. This register is a 2’s complement, left-justified. The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation.
Page 497: Temperature Sensor
Chapter 28 Analog-to-Digital Converter (ADC) 28.4.8 Temperature sensor The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs. The following equation provides an approximate transfer function of the temperature sensor. Figure 28-63. Approximate transfer function of the temperature sensor where: •...
Page 498: Mcu Normal Stop Mode Operation
Functional description The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in Wait mode. The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU. See the Chip Configuration information on ALTCLK specific to this MCU.
Page 499: Mcu Low-Power Stop Mode Operation
Chapter 28 Analog-to-Digital Converter (ADC) If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Normal Stop mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. The result register, Rn, will contain the data from the first completed conversion that occurred during Normal Stop mode.
Page 500: Kl25 Sub-Family Reference Manual, Rev. 3, September
Initialization information 28.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is: 1. Calibrate the ADC by following the calibration instructions in Calibration function. 2. Update CFG to select the input clock source and the divide ratio used to generate ADCK.
Page 501: Application Information
Chapter 28 Analog-to-Digital Converter (ADC) Bit 7 COCO Read-only flag which is set when a conversion completes. Bit 6 AIEN Conversion complete interrupt enabled. Bit 5 DIFF Single-ended conversion selected. Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion.
Page 502: Freescale Semiconductor, Inc
Application information 28.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: • V and V available as separate pins—When available on a separate pin, both and V must be connected to the same voltage potential as their corresponding MCU digital supply, V...
Page 503: Sources Of Error
Chapter 28 Analog-to-Digital Converter (ADC) AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good high-frequency characteristics.
Page 504: Freescale Semiconductor, Inc
Application information RAS = External analog source resistance SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2 LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time.
Page 505: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) • For software triggered conversions, immediately follow the write to SC1 with a Wait instruction or Stop instruction. • For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces V noise but increases effective conversion time due to stop recovery.
Page 506: Freescale Semiconductor, Inc
Application information For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB. 28.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: •...
Page 507: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. • Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage.
Page 508: Freescale Semiconductor, Inc
Application information KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 509: Introduction
Chapter 29 Comparator (CMP) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation.
Page 510: Bit Dac Key Features
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications •...
Page 511: Anmux Key Features
Chapter 29 Comparator (CMP) 29.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 29.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. KL25 Sub-Family Reference Manual, Rev.
Page 512: Cmp Block Diagram
CMP block diagram VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 29-1. CMP, DAC and ANMUX block diagram 29.6 CMP block diagram The following figure shows the block diagram for the CMP module.
Page 513: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSCTRL[1:0] Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided prescaler FILT_PER CGMUX clock Figure 29-2. Comparator module block diagram In the CMP block diagram: •...
Page 514: Memory Map/Register Definitions
Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. •...
Page 515: Cmp Control Register 1 (Cmpx_Cr1)
Chapter 29 Comparator (CMP) CMPx_CR0 field descriptions (continued) Field Description 5 consecutive samples must agree. 6 consecutive samples must agree. 7 consecutive samples must agree. This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 516: Freescale Semiconductor, Inc
Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received.
Page 517: Cmp Filter Period Register (Cmpx_Fpr)
Chapter 29 Comparator (CMP) 29.7.3 CMP Filter Period Register (CMPx_FPR) Address: 4007_3000h base + 2h offset = 4007_3002h Read FILT_PER Write Reset CMPx_FPR field descriptions Field Description 7–0 Filter Sample Period FILT_PER Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter.
Page 518: Dac Control Register (Cmpx_Daccr)
Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. Interrupt is disabled.
Page 519: Mux Control Register (Cmpx_Muxcr)
Chapter 29 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in 5–0 DAC Output Voltage Select VOSEL Selects an output voltage from one of 64 distinct levels. /64) * (VOSEL[5:0] + 1) , so the DACO range is from V /64 to V DACO = (V...
Page 520: Functional Description
Functional description CMPx_MUXCR field descriptions (continued) Field Description NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 29.8 Functional description The CMP module can be used to compare two analog input voltages applied to INP and INM.
Page 521: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications.
Page 522: Freescale Semiconductor, Inc
Functional description For cases where a comparator is used to drive a fault input, for example, for a motor- control module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry.
Page 523: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) NOTE See the chip configuration section for the source of sample/ window input. The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed.
Page 524: Freescale Semiconductor, Inc
Functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived.
Page 525: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0] > 0x01 Polarity Interrupt Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1...
Page 526: Freescale Semiconductor, Inc
Functional description Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSTCTR[1:0 > 0x01 Polarity Filter Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=0 Figure 29-19.
Page 527: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 29-20. Windowed mode operation Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSCTR[1:0] 0x01 Interrupt Polarity Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock...
Page 528: Freescale Semiconductor, Inc
Functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 29.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 29-20, and adds resampling of COUTA to generate COUT.
Page 529: Power Modes
Chapter 29 Comparator (CMP) 29.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function.
Page 530: Startup And Operation
Functional description 29.8.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 531: Low-Pass Filter
Chapter 29 Comparator (CMP) The time required to stabilize COUT will be the power-on delay of the comparators plus the largest propagation delay from a selected analog source through the analog comparator, windowing function and filter. See the Data Sheets for power-on delays of the comparators.
Page 532: Freescale Semiconductor, Inc
Functional description The filter output will be at logic 0 when first initalized, and will subsequently change when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1.
Page 533: Cmp Interrupts
Chapter 29 Comparator (CMP) Table 29-16. Comparator sample/filter maximum latencies (continued) CR1[ CR1[ CR1[ CR0[FILTER FPR[FILT_P Mode # Operation Maximum latency _CNT] 0x00 Continuous Mode 0x00 0x01 Sampled, Non-Filtered mode SAMPLE 0x01 > 0x00 + (FPR[FILT_PER] * ) + T >...
Page 534: Cmp Asyncrhonous Dma Support
CMP Asyncrhonous DMA support transfer request rather than a CPU interrupt instead. When the DMA has completed the transfer, it sends a transfer completing indicator that deasserts the DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request.
Page 535: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 29 Comparator (CMP) DACEN VOSEL[5:0] VRSEL DACO Figure 29-24. 6-bit DAC block diagram 29.13 DAC functional description This section provides DAC functional description. 29.13.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder •...
Page 536: Dac Interrupts
DAC interrupts 29.16 DAC interrupts This module has no interrupts. 29.17 CMP Trigger Mode CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the CMP must be enabled. If the DAC is to be used as a reference to the CMP, it must also be enabled.
Page 537: Introduction
Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 12-bit digital-to-analog converter (DAC) is a low-power general-purpose DAC. The output of this DAC can be placed on an external pin or set as one of the inputs to the analog comparator, analog-to-digital converter (ADC), or other peripherals.
Page 538: Freescale Semiconductor, Inc
Block diagram DACREF_2 DACREF_1 DACRFS DACRFS AMP buffer DACEN LPEN DACDAT[11:0] Hardware trigger DACBFWMF & DACBWIEN DACSWTRG Data Buffer DACBFWM DACBFRPTF dac_interrupt & DACBFEN DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 30-1. DAC block diagram KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 539: Memory Map/Register Definition
Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. The address of a register is the sum of a base address and an address offset. The base address is defined at the chip level.
Page 540: Dac Data High Register (Dacx_Datnh)
Memory map/register definition 30.4.2 DAC Data High Register (DACx_DATnH) Address: 4003_F000h base + 1h offset + (2d × i), where i=0d to 1d Read DATA1 Write Reset DACx_DATnH field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–0 When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following DATA1...
Page 541: Dac Control Register (Dacx_C0)
Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.4.4 DAC Control Register (DACx_C0) Address: 4003_F000h base + 21h offset = 4003_F021h Read DACTRGSE DACEN DACRFS LPEN DACBTIEN DACBBIEN Write DACSWTRG Reset DACx_C0 field descriptions Field Description DAC Enable DACEN Starts the Programmable Reference Generator operation. The DAC system is disabled.
Page 542: Dac Control Register 1 (Dacx_C1)
Memory map/register definition 30.4.5 DAC Control Register 1 (DACx_C1) Address: 4003_F000h base + 22h offset = 4003_F022h Read DMAEN DACBFMD DACBFEN Write Reset DACx_C1 field descriptions Field Description DMA Enable Select DMAEN DMA is disabled. DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
Page 543: Functional Description
Chapter 30 12-bit Digital-to-Analog Converter (DAC) DACx_C2 field descriptions (continued) Field Description 3–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC Buffer Upper Limit DACBFUP Selects the upper limit of the DAC buffer. The buffer read pointer cannot exceed it. 30.5 Functional description The 12-bit DAC module can select one of the two reference inputs—DACREF_1 and DACREF_2 as the DAC reference voltage, V...
Page 544: Dma Operation
Functional description 30.5.1.2 Modes of DAC data buffer operation The following table describes the different modes of data buffer operation for the DAC module. Table 30-23. Modes of DAC data buffer operation Modes Description This is the default mode. The buffer works as a circular buffer. The read pointer increases by one, every time the trigger Buffer Normal mode occurs.
Page 545: Freescale Semiconductor, Inc
Chapter 30 12-bit Digital-to-Analog Converter (DAC) Table 30-24. Modes of operation (continued) Modes of operation Description If enabled, the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop. Stop mode In low-power stop modes, the DAC is fully shut down.
Page 546: Freescale Semiconductor, Inc
Functional description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 547: Introduction
Chapter 31 Timer/PWM Module (TPM) 31.1 Introduction The TPM (Timer/PWM Module) is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes.
Page 548: Modes Of Operation
Introduction • It can be a free-running counter or modulo counter • The counting can be up or up-down • Includes 6 channels that can be configured for input capture, output compare, or edge-aligned PWM mode • In input capture mode the capture can occur on rising edges, falling edges or both edges •...
Page 549: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 31 Timer/PWM Module (TPM) The following figure shows the TPM structure. The central component of the TPM is the 16-bit counter with programmable final value and its counting can be up or up-down. CMOD no clock selected (counter disable) module clock prescaler external clock...
Page 550: Tpm_Extclk — Tpm External Clock
Memory Map and Register Definition 31.2.1 TPM_EXTCLK — TPM External Clock The rising edge of the external input signal is used to increment the TPM counter if selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of the TPM counter clock frequency.
Page 551: Freescale Semiconductor, Inc
Chapter 31 Timer/PWM Module (TPM) TPM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_9000 Status and Control (TPM1_SC) 0000_0000h 31.3.1/552 4003_9004 Counter (TPM1_CNT) 0000_0000h 31.3.2/553 4003_9008 Modulo (TPM1_MOD) 0000_FFFFh 31.3.3/554 4003_900C Channel (n) Status and Control (TPM1_C0SC) 0000_0000h 31.3.4/555 4003_9010...
Page 552: Status And Control (Tpmx_Sc)
Memory Map and Register Definition 31.3.1 Status and Control (TPMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, module configuration and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE CMOD...
Page 553: Counter (Tpmx_Cnt)
Chapter 31 Timer/PWM Module (TPM) TPMx_SC field descriptions (continued) Field Description LPTPM counter has not overflowed. LPTPM counter has overflowed. Timer Overflow Interrupt Enable TOIE Enables LPTPM overflow interrupts. Disable TOF interrupts. Use software polling or DMA request. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-aligned PWM Select CPWMS Selects CPWM mode.
Page 554: Modulo (Tpmx_Mod)
Memory Map and Register Definition Reading the CNT register adds two wait states to the register access due to synchronization delays. Address: Base address + 4h offset COUNT Reset TPMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 555: Channel (N) Status And Control (Tpmx_Cnsc)
Chapter 31 Timer/PWM Module (TPM) 31.3.4 Channel (n) Status and Control (TPMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. When switching from one channel mode to a different channel mode, the channel must first be disabled and this must be acknowledged in the LPTPM counter clock domain.
Page 556: Freescale Semiconductor, Inc
Memory Map and Register Definition CHIE MSB MSA ELSB ELSA Reset TPMx_CnSC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel Flag Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect.
Page 557: Channel (N) Value (Tpmx_Cnv)
Chapter 31 Timer/PWM Module (TPM) 31.3.5 Channel (n) Value (TPMx_CnV) These registers contain the captured LPTPM counter value for the input modes or the match value for the output modes. In input capture mode, any write to a CnV register is ignored. In compare modes, writing to a CnV register latches the value into a buffer.
Page 558: Freescale Semiconductor, Inc
Memory Map and Register Definition Address: Base address + 50h offset Reset Reset TPMx_STATUS field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Timer Overflow Flag See register description LPTPM counter has not overflowed.
Page 559: Configuration (Tpmx_Conf)
Chapter 31 Timer/PWM Module (TPM) TPMx_STATUS field descriptions (continued) Field Description Channel 2 Flag CH2F See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag CH1F See the register description. No channel event has occurred. A channel event has occurred.
Page 560: Freescale Semiconductor, Inc
Memory Map and Register Definition TPMx_CONF field descriptions (continued) Field Description 27–24 Trigger Select TRGSEL Selects the input trigger to use for starting the counter and/or reloading the counter. This field should only be changed when the LPTPM counter is disabled. See Chip configuration section for available options. 23–19 This field is reserved.
Page 561: Functional Description
Chapter 31 Timer/PWM Module (TPM) TPMx_CONF field descriptions (continued) Field Description Configures the LPTPM behavior in debug mode. All other configurations are reserved. LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. LPTPM counter continues in debug mode.
Page 562: Prescaler
Functional Description The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter by writing zero to the CMOD[1:0] bits does not affect the TPM counter value or other registers, but must be acknowledged by the TPM counter clock domain before they read as zero.
Page 563: Freescale Semiconductor, Inc
Chapter 31 Timer/PWM Module (TPM) The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with zero. The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock.
Page 564: Input Capture Mode
Functional Description MOD = 0x0004 Timer module counter TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = 2 x MOD x period of timer module counter clock Figure 31-80. Example of Up-Down Counting 31.4.3.3 Counter Reset Any write to CNT resets the TPM counter and the channel outputs to their initial values (except for channels in output compare mode).
Page 565: Output Compare Mode
Chapter 31 Timer/PWM Module (TPM) was rising edge selected? CHnIE channel (n) interrupt CHnF synchronizer rising edge channel (n) input edge detector timer module clock falling edge was falling edge selected? timer module counter Figure 31-81. Input capture mode The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input.
Page 566: Freescale Semiconductor, Inc
Functional Description MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow match match overflow overflow previous value channel (n) output previous value CHnF bit TOF bit Figure 31-82. Example of the output compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003...
Page 567: Edge-Aligned Pwm (Epwm) Mode
Chapter 31 Timer/PWM Module (TPM) 31.4.6 Edge-Aligned PWM (EPWM) Mode The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0). The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is determined by CnV. The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV), that is, at the end of the pulse width.
Page 568: Center-Aligned Pwm (Cpwm) Mode
Functional Description MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output previous value CHnF bit TOF bit Figure 31-87. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV >...
Page 569: Freescale Semiconductor, Inc
Chapter 31 Timer/PWM Module (TPM) timer module counter = 0 channel (n) match channel (n) match counter overflow counter overflow (timer module counting (timer module counting timer module counter = timer module counter = is down) is up) channel (n) output pulse width (2 x CnV) period...
Page 570: Registers Updated From Write Buffers
Functional Description If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal. If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal, although the CHnF bit is set when the counter changes from incrementing to decrementing.
Page 571: Reset Overview
Chapter 31 Timer/PWM Module (TPM) 31.4.9 DMA The channel generates a DMA transfer request according to DMA and CHnIE bits (see the following table). Table 31-110. Channel DMA Transfer Request CHnIE Channel DMA Transfer Request Channel Interrupt The channel DMA transfer request is not The channel interrupt is not generated.
Page 572: Freescale Semiconductor, Inc
Functional Description 31.4.11.1 Timer Overflow Interrupt The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 31.4.11.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 573: Introduction
Chapter 32 Periodic Interrupt Timer (PIT) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels.
Page 574: Features
Signal description Peripheral registers load_value Timer 1 I i nterrupts Triggers Timer n Peripheral bus clock Figure 32-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 32.1.2 Features The main features of this block are: •...
Page 575: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 32 Periodic Interrupt Timer (PIT) 32.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE • Reserved registers will read as 0, writes will have no effect. • See the chip configuration details for the number of PIT channels used in this MCU. Table 32-2.
Page 576: Freescale Semiconductor, Inc
Memory map/register description Address: 4003_7000h base + 0h offset = 4003_7000h Reset MDIS Reset PIT_MCR field descriptions Field Description 0–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved Module Disable - (PIT section) MDIS...
Page 577: Pit Upper Lifetime Timer Register (Pit_Ltmr64H)
Chapter 32 Periodic Interrupt Timer (PIT) 32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H) This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer. Address: 4003_7000h base + E0h offset = 4003_70E0h Reset PIT_LTMR64H field descriptions Field Description...
Page 578: Timer Load Value Register (Pit_Ldvaln)
Memory map/register description 32.3.4 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts. Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d Reset PIT_LDVALn field descriptions Field Description 0–31 Timer Start Value Sets the timer start value.
Page 579: Timer Control Register (Pit_Tctrln)
Chapter 32 Periodic Interrupt Timer (PIT) 32.3.6 Timer Control Register (PIT_TCTRLn) These register contain the control bits for each timer. Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1d Reset Reset PIT_TCTRLn field descriptions Field Description 0–28 This field is reserved.
Page 580: Timer Flag Register (Pit_Tflgn)
Functional description 32.3.7 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 1d Reset Reset PIT_TFLGn field descriptions Field Description 0–30 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 581: Freescale Semiconductor, Inc
Chapter 32 Periodic Interrupt Timer (PIT) 32.4.1.1 Timers The timers generate triggers at periodic intervals, when enabled. The timers load the start values as specified in their LDVAL registers, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag.
Page 582: Interrupts
Initialization and application information Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 32-19. Dynamically setting a new load value 32.4.1.2 Debug mode In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation.
Page 583: Example Configuration For Chained Timers
Chapter 32 Periodic Interrupt Timer (PIT) • Timer 1 creates an interrupt every 5.12 ms. • Timer 3 creates a trigger event every 30 ms. The PIT module must be activated by writing a 0 to MCR[MDIS]. The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.
Page 584: Example Configuration For The Lifetime Timer
Example configuration for the lifetime timer The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do. So, Timer 1 is set up to trigger every 6 s (600 million cycles).
Page 585: Freescale Semiconductor, Inc
Chapter 32 Periodic Interrupt Timer (PIT) PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; KL25 Sub-Family Reference Manual, Rev.
Page 586: Freescale Semiconductor, Inc
Example configuration for the lifetime timer KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 587: Introduction
Chapter 33 Low-Power Timer (LPTMR) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes.
Page 588: Lptmr Signal Descriptions
LPTMR signal descriptions Table 33-1. Modes of operation Modes Description The LPTMR operates normally. The LPTMR continues to operate normally and Wait may be configured to exit the low-power mode by generating an interrupt request. The LPTMR continues to operate normally and Stop may be configured to exit the low-power mode by generating an interrupt request.
Page 589: Low Power Timer Control Status Register (Lptmrx_Csr)
Chapter 33 Low-Power Timer (LPTMR) LPTMR memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 0000_0000h 33.3.1/589 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 0000_0000h 33.3.2/590 4004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 0000_0000h...
Page 590: Low Power Timer Prescale Register (Lptmrx_Psr)
Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description Pulse counter input 1 is selected. Pulse counter input 2 is selected. Pulse counter input 3 is selected. Timer Pin Polarity Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the LPTMR is disabled.
Page 591: Freescale Semiconductor, Inc
Chapter 33 Low-Power Timer (LPTMR) LPTMRx_PSR field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–3 Prescale Value PRESCALE Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter mode.
Page 592: Low Power Timer Compare Register (Lptmrx_Cmr)
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description Prescaler/glitch filter clock 0 selected. Prescaler/glitch filter clock 1 selected. Prescaler/glitch filter clock 2 selected. Prescaler/glitch filter clock 3 selected. 33.3.3 Low Power Timer Compare Register (LPTMRx_CMR) Address: 4004_0000h base + 8h offset = 4004_0008h COMPARE Reset LPTMRx_CMR field descriptions...
Page 593: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 33 Low-Power Timer (LPTMR) 33.4 Functional description 33.4.1 LPTMR power and reset The LPTMR remains powered in all power modes, including low-leakage modes. If the LPTMR is not required to remain operating during a low-power mode, then it must be disabled before entering the mode.
Page 594: Freescale Semiconductor, Inc
Functional description NOTE The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled. 33.4.3.1 Prescaler enabled In Time Counter mode, when the prescaler is enabled, the output of the prescaler directly clocks the CNR. When the LPTMR is enabled, the CNR will increment every 2 to 2 prescaler clock cycles.
Page 595: Lptmr Compare
Chapter 33 Low-Power Timer (LPTMR) 33.4.3.4 Glitch filter bypassed In Pulse Counter mode, when the glitch filter is bypassed, the selected input source increments the CNR every time it asserts. Before the LPTMR is first enabled, the selected input source is forced to be asserted. This prevents the CNR from incrementing if the selected input source is already asserted when the LPTMR is first enabled.
Page 596: Lptmr Hardware Trigger
Functional description 33.4.6 LPTMR hardware trigger The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be used to trigger hardware events in other peripherals without software intervention. The hardware trigger is always enabled. When Then The CMR is set to 0 with CSR[TFC] clear The LPTMR hardware trigger will assert on the first compare...
Page 597: Introduction
Chapter 34 Real Time Clock (RTC) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 34.1.1 Features The RTC module features include: • 32-bit seconds counter with roll-over protection and 32-bit alarm •...
Page 598: Rtc Signal Descriptions
Register definition 34.1.3 RTC Signal Descriptions Table 34-1. RTC signal descriptions Signal Description RTC_CLKOUT 1 Hz square-wave output 34.1.3.1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz square wave output. 34.2 Register definition All registers must be accessed using 32-bit writes and all register accesses incur three wait states.
Page 599: Rtc Time Seconds Register (Rtc_Tsr)
Chapter 34 Real Time Clock (RTC) 34.2.1 RTC Time Seconds Register (RTC_TSR) Address: 4003_D000h base + 0h offset = 4003_D000h Reset RTC_TSR field descriptions Field Description 31–0 Time Seconds Register When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set.
Page 600: Rtc Time Alarm Register (Rtc_Tar)
Register definition 34.2.3 RTC Time Alarm Register (RTC_TAR) Address: 4003_D000h base + 8h offset = 4003_D008h Reset RTC_TAR field descriptions Field Description 31–0 Time Alarm Register When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments.
Page 601: Rtc Control Register (Rtc_Cr)
Chapter 34 Real Time Clock (RTC) RTC_TCR field descriptions (continued) Field Description Time Prescaler Register overflows every 32896 clock cycles. Time Prescaler Register overflows every 32769 clock cycles. Time Prescaler Register overflows every 32768 clock cycles. Time Prescaler Register overflows every 32767 clock cycles. Time Prescaler Register overflows every 32641 clock cycles.
Page 602: Freescale Semiconductor, Inc
Register definition RTC_CR field descriptions (continued) Field Description This field is reserved. Reserved It must always be written to 0. Oscillator 2pF Load Configure SC2P Disable the load. Enable the additional load. Oscillator 4pF Load Configure SC4P Disable the load. Enable the additional load.
Page 603: Rtc Status Register (Rtc_Sr)
Chapter 34 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description No effect. Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. 34.2.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Reset Reset...
Page 604: Rtc Lock Register (Rtc_Lr)
Register definition RTC_SR field descriptions (continued) Field Description Time Invalid Flag The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled. Time is valid.
Page 605: Rtc Interrupt Enable Register (Rtc_Ier)
Chapter 34 Real Time Clock (RTC) RTC_LR field descriptions (continued) Field Description Time Compensation Lock After being cleared, this bit can be set only by POR or software reset. Time Compensation Register is locked and writes are ignored. Time Compensation Register is not locked and writes complete as normal. 2–0 This field is reserved.
Page 606: Functional Description
Functional description RTC_IER field descriptions (continued) Field Description Seconds interrupt is disabled. Seconds interrupt is enabled. This field is reserved. Reserved Time Alarm Interrupt Enable TAIE Time alarm flag does not generate an interrupt. Time alarm flag does generate an interrupt. Time Overflow Interrupt Enable TOIE Time overflow flag does not generate an interrupt.
Page 607: Time Counter
Chapter 34 Real Time Clock (RTC) 34.3.1.2 Software reset Writing one to the CR[SWR] forces the equivalent of a POR to the rest of the RTC module. The CR[SWR] is not affected by the software reset and must be cleared by software.
Page 608: Time Alarm
Functional description register. The RTC itself does not calculate the amount of compensation that is required, although the 1 Hz clock is output to an external pin in support of external calibration logic. Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount.
Page 609: Update Mode
Chapter 34 Real Time Clock (RTC) 34.3.5 Update mode The Update Mode bit in the Control register (CR[UM]) configures software write access to the Time Counter Enable (SR[TCE]) bit. When CR[UM] is clear, SR[TCE] can be written only when the LR[SRL] bit is set. When CR[UM] is set, the SR[TCE] can also be written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set.
Page 610: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional description KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 611: Introduction
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This section describes the USB. The OTG implementation in this module provides limited host functionality and device solutions for implementing a USB 2.0 full-speed/ low-speed compliant peripheral.
Page 612: Usb On-The-Go
Introduction The host initiates transactions to specific peripherals, whereas the device responds to control transactions. The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mbit/s or 1.5 Mbit/s.
Page 613: Usb-Fs Features
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) Print Photos Keyboard Input Swap Songs Hot Sync Figure 35-2. Example USB 2.0 On-The-Go configurations 35.1.3 USB-FS Features • USB 1.1 and 2.0 compliant full-speed device controller • 16 bidirectional end points •...
Page 614: Programmers Interface
Programmers interface 35.2.1 Data Structures The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications the USB-FS implements a Buffer Descriptor Table (BDT) in system memory. See Figure 35-3.
Page 615: Rx Vs. Tx As A Usb Target Device Or Usb Host
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) System Memory BDT Page BDT_PAGE Registers END_POINT Current Endpoint Start of Buffer Buffer in Memory Figure 35-3. Buffer descriptor table 35.3.2 RX vs. TX as a USB target device or USB host The USB-FS core uses software control to switch between two modes of operation: •...
Page 616: Addressing Bdt Entries
Programmers interface 35.3.3 Addressing BDT entries An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via the USB-FS or microprocessor. Some points of interest are: • The BDT occupies up to 512 bytes of system memory. •...
Page 617: Freescale Semiconductor, Inc
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) • Who owns the buffer in system memory • Data0 or Data1 PID • Whether to release ownership upon packet completion • No address increment (FIFO mode) • Whether data toggle synchronization is enabled •...
Page 618: Freescale Semiconductor, Inc
Programmers interface Table 35-4. Buffer descriptor fields (continued) Field Description Determines whether the processor or the USB-FS currently owns the buffer. Except when KEEP=1, the SIE hands ownership back to the processor after completing the token by clearing this bit. This must always be the last byte of the BD that the processor updates when it initializes a BD.
Page 619: Usb Transaction
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) Table 35-4. Buffer descriptor fields (continued) Field Description TOK_PID[n] Bits [5:2] can also represent the current token PID. The current token PID is written back in to the BD by the USB-FS when a transfer completes. The values written back are the token PID values from the USB specification: •...
Page 620: Freescale Semiconductor, Inc
Programmers interface USB RST USB_RST SOF Interrupt Generated Interrupt Generated SETUP TOKEN DATA TOK_DNE Interrupt Generated IN TOKEN DATA TOK_DNE Interrupt Generated OUT TOKEN DATA TOK_DNE USB Host Function Interrupt Generated Figure 35-4. USB token transaction The USB has two sources for the DMA overrun error: Memory Latency The memory latency may be too high and cause the receive FIFO to overflow.
Page 621: Memory Map/Register Definitions
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) Table 35-5. USB responses to DMA overrun errors (continued) Errors due to Memory Latency Errors due to Oversized Packets • For host mode, the TOKDNE interrupt is generated and The packet length field written back to the BDT is the the TOK_PID field of the BDT is 1111 to indicate the MaxPacket value that represents the length of the clipped DMA latency error.
Page 622: Freescale Semiconductor, Inc
Memory map/Register definitions USB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 35.4.16/ 4007_209C BDT Page Register 1 (USB0_BDTPAGE1) 35.4.17/ 4007_20A0 Frame Number Register Low (USB0_FRMNUML) 35.4.18/ 4007_20A4 Frame Number Register High (USB0_FRMNUMH) 35.4.19/ 4007_20A8 Token register (USB0_TOKEN)
Page 623: Peripheral Id Register (Usbx_Perid)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 35.4.23/ 4007_20FC Endpoint Control register (USB0_ENDPT15) 35.4.24/ 4007_2100 USB Control register (USB0_USBCTRL) 35.4.25/ 4007_2104 USB OTG Observe register (USB0_OBSERVE) 35.4.26/ 4007_2108 USB OTG Control register (USB0_CONTROL)
Page 624: Peripheral Id Complement Register (Usbx_Idcomp)
Memory map/Register definitions 35.4.2 Peripheral ID Complement register (USBx_IDCOMP) Reads back the complement of the Peripheral ID register. For the USB peripheral, the value is 0xFB. Address: 4007_2000h base + 4h offset = 4007_2004h Read Write Reset USBx_IDCOMP field descriptions Field Description 7–6...
Page 625: Peripheral Additional Info Register (Usbx_Addinfo)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 35.4.4 Peripheral Additional Info register (USBx_ADDINFO) Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with the Host Enable bit. Address: 4007_2000h base + Ch offset = 4007_200Ch Read IRQNUM IEHOST Write...
Page 626: Otg Interrupt Control Register (Usbx_Otgicr)
Memory map/Register definitions USBx_OTGISTAT field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid. SESSVLDCHG This bit is set when a change in VBUS is detected on a B device.
Page 627: Otg Status Register (Usbx_Otgstat)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGICR field descriptions (continued) Field Description Disables the B_SESS_CHG interrupt. Enables the B_SESS_CHG interrupt. This field is reserved. Reserved This read-only field is reserved and always has the value 0. A VBUS Valid Interrupt Enable AVBUSEN Disables the AVBUSCHG interrupt.
Page 628: Otg Control Register (Usbx_Otgctl)
Memory map/Register definitions USBx_OTGSTAT field descriptions (continued) Field Description B Session End BSESSEND The VBUS voltage is above the B session end threshold. The VBUS voltage is below the B session end threshold. This field is reserved. Reserved This read-only field is reserved and always has the value 0. A VBUS Valid AVBUSVLD The VBUS voltage is below the A VBUS Valid threshold.
Page 629: Interrupt Status Register (Usbx_Istat)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGCTL field descriptions (continued) Field Description If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D– Data Line pull-down resistors are engaged. The pull-up and pull-down controls in this register are used.
Page 630: Interrupt Enable Register (Usbx_Inten)
Memory map/Register definitions USBx_ISTAT field descriptions (continued) Field Description In Host mode this field is set when the SOF threshold is reached, so that software can prepare for the next SOF. This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur. The ERROR processor must then read the ERRSTAT register to determine the source of the error.
Page 631: Error Interrupt Status Register (Usbx_Errstat)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_INTEN field descriptions (continued) Field Description Disbles the SOFTOK interrupt. Enables the SOFTOK interrupt. ERROR Interrupt Enable ERROREN Disables the ERROR interrupt. Enables the ERROR interrupt. USBRST Interrupt Enable USBRSTEN Disables the USBRST interrupt. Enables the USBRST interrupt.
Page 632: Error Interrupt Enable Register (Usbx_Erren)
Memory map/Register definitions USBx_ERRSTAT field descriptions (continued) Field Description OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. This bit is set if the data field received was not 8 bits in length.
Page 633: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_ERREN field descriptions (continued) Field Description BTOERR Interrupt Enable BTOERREN Disables the BTOERR interrupt. Enables the BTOERR interrupt. DFN8 Interrupt Enable DFN8EN Disables the DFN8 interrupt. Enables the DFN8 interrupt. CRC16 Interrupt Enable CRC16EN Disables the CRC16 interrupt.
Page 634: Control Register (Usbx_Ctl)
Memory map/Register definitions USBx_STAT field descriptions Field Description 7–4 This four-bit field encodes the endpoint address that received or transmitted the previous token. This ENDP allows the processor core to determine the BDT entry that was updated by the last USB transaction. Transmit Indicator The most recent transaction was a receive operation.
Page 635: Address Register (Usbx_Addr)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_CTL field descriptions (continued) Field Description When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the HOSTMODEEN USB module performs USB transactions under the programmed control of the host processor. When set to 1 this bit enables the USB Module to execute resume signaling.
Page 636: Bdt Page Register 1 (Usbx_Bdtpage1)
Memory map/Register definitions 35.4.16 BDT Page Register 1 (USBx_BDTPAGE1) Provides address bits 15 through 9 of the base address where the current Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always zero.
Page 637: Frame Number Register High (Usbx_Frmnumh)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 35.4.18 Frame Number Register High (USBx_FRMNUMH) Contains an 11-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. Address: 4007_2000h base + A4h offset = 4007_20A4h Read FRM[10:8] Write...
Page 638: Sof Threshold Register (Usbx_Softhld)
Memory map/Register definitions USBx_TOKEN field descriptions (continued) Field Description 0001 OUT Token. USB Module performs an OUT (TX) transaction. 1001 IN Token. USB Module performs an In (RX) transaction. 1101 SETUP Token. USB Module performs a SETUP (TX) transaction 3–0 Holds the Endpoint address for the token command.
Page 639: Bdt Page Register 2 (Usbx_Bdtpage2)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 35.4.21 BDT Page Register 2 (USBx_BDTPAGE2) Contains an 8-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. Address: 4007_2000h base + B0h offset = 4007_20B0h Read BDTBA Write...
Page 640: Usb Control Register (Usbx_Usbctrl)
Memory map/Register definitions In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers.
Page 641: Usb Otg Observe Register (Usbx_Observe)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_USBCTRL field descriptions Field Description Places the USB transceiver into the suspend state. SUSP USB transceiver is not in suspend state. USB transceiver is in suspend state. Enables the weak pulldowns on the USB transceiver. Weak pulldowns are disabled on D+ and D–.
Page 642: Usb Otg Control Register (Usbx_Control)
Memory map/Register definitions 35.4.26 USB OTG Control register (USBx_CONTROL) Address: 4007_2000h base + 108h offset = 4007_2108h Read DPPULLUPNONOTG Write Reset Read Write Reset USBx_CONTROL field descriptions Field Description 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Provides control of the DP Pullup in the USB OTG module, if USB is configured in non-OTG device DPPULLUPNONOTG mode.
Page 643: Frame Adjust Register (Usbx_Usbfrmadjust)
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) USBx_USBTRC0 field descriptions (continued) Field Description NOTE: This bit is always read as zero. Wait two USB clock cycles after setting this bit. Normal USB module operation. Returns the USB module to its reset state. This field is reserved.
Page 644: Otg And Host Mode Operation
OTG and Host mode operation 35.5 OTG and Host mode operation The Host mode logic allows devices such as digital cameras and palmtop computers to function as a USB Host Controller. The OTG logic adds an interface to allow the OTG Host Negotiation and Session Request Protocols (HNP and SRP) to be implemented in software.
Page 645: Freescale Semiconductor, Inc
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 2. Enable the ATTACH interrupt (INT_ENB[ATTACH]=1). 3. Wait for ATTACH interrupt (INT_STAT[ATTACH]). Signaled by USB Target pull- up resistor changing the state of DPLUS or DMINUS from 0 to 1 (SE0 to J or K state).
Page 646: Freescale Semiconductor, Inc
Host Mode Operation Examples complete. When the BDT is written, a token done (ISTAT[TOKDNE]) interrupt is asserted. This completes the setup phase of the setup transaction. Se the Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework" (http:// www.usb.org/developers/docs).
Page 647: On-The-Go Operation
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) 1. Complete all steps to discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant.
Page 648: Otg Dual Role A Device Operation
On-The-Go operation 35.7.1 OTG dual role A device operation A device is considered the A device because of the type of cable attached. If the USB Type A connector or the USB Type Mini A connector is plugged into the device, it is considered the A device.
Page 649: Otg Dual Role B Device Operation
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) Table 35-96. State descriptions for the dual role A device flow (continued) State Action Response A_WAIT_BCON After 200 ms without Attach or ID Interrupt. (This could wait forever Go to A_WAIT_FALL if desired.) Turn off DRV_VBUS A_VBUS_VLD Interrupt and B device attaches Go to A_HOST...
Page 650: Freescale Semiconductor, Inc
On-The-Go operation B_IDLE A_IDLE B_HOST B_SRP_INIT B_WAIT_ACON B_PERIPHERAL Figure 35-94. Dual role B device flow diagram Table 35-97. State descriptions for the dual role B device flow State Action Response B_IDLE If ID\ Interrupt. Go to A_IDLE A Type A cable has been plugged in and the device should now respond as a Type A device.
Page 651: Introduction
Chapter 36 USB Voltage Regulator 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel.
Page 652: Overview
Introduction 36.1.1 Overview A simplified block diagram for the USB Voltage Regulator module is shown below. STANDBY Regulator Other Modules STANDBY Regulated Output reg33_out Voltage reg33_in Power RUN Regulator Supply ESR: 5m -> 100m Ohms Voltage Regulator Voltage Regulator External Capacitor Chip typical = 2.2uF Figure 36-2.
Page 653: Modes Of Operation
Chapter 36 USB Voltage Regulator • Automatic power-up once some voltage is applied to the regulator input. • Pass-through mode for regulator input voltages less than 3.6 V • Small output capacitor: 2.2 uF • Stable with aluminum, tantalum or ceramic capacitors. 36.1.3 Modes of Operation The regulator has these power modes: •...
Page 654: Kl25 Sub-Family Reference Manual, Rev. 3, September
USB Voltage Regulator Module Signal Descriptions KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 655: Introduction
Chapter 37 Serial Peripheral Interface (SPI) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others.
Page 656: Modes Of Operation
Introduction • Programmable transmit bit rate • Double-buffered transmit and receive data register • Serial clock phase and polarity options • Slave select output • Mode fault error flag with CPU interrupt capability • Control of SPI operation during wait mode •...
Page 657: Block Diagrams
Chapter 37 Serial Peripheral Interface (SPI) The SPI is completely disabled in stop modes where the peripheral bus clock is stopped and internal logic states are not retained. When the CPU wakes from these stop modes, all SPI register content is reset. Detailed descriptions of operating modes appear in Low Power Mode Options.
Page 658: Freescale Semiconductor, Inc
Introduction 37.1.3.2 SPI Module Block Diagram The following is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPIx_D) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in 8 bits of data, the data is transferred into the double-buffered receiver where it can be read from SPIx_D.
Page 659: External Signal Description
Chapter 37 Serial Peripheral Interface (SPI) PIN CONTROL MOSI (MOMI) Tx BUFFER (WRITE SPIxD) ENABLE MISO SPI SYSTEM (SISO) SPI SHIFT REGISTER SHIFT SHIFT Rx BUFFER (READ SPIxD) SPC0 BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK BUS RATE...
Page 660: Spsck — Spi Serial Clock
External Signal Description 37.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 37.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output.
Page 661: Memory Map And Register Descriptions
Chapter 37 Serial Peripheral Interface (SPI) 37.3 Memory Map and Register Descriptions The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Absolute Address...
Page 662: Freescale Semiconductor, Inc
Memory Map and Register Descriptions SPI0_C1 field descriptions (continued) Field Description Interrupts from SPRF and MODF are inhibited—use polling Request a hardware interrupt when SPRF or MODF is 1 SPI system enable This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
Page 663: Spi Control Register 2 (Spix_C2)
Chapter 37 Serial Peripheral Interface (SPI) SPI0_C1 field descriptions (continued) Field Description LSB first (shifter direction) LSBFE This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. SPI serial data transfers start with most significant bit SPI serial data transfers start with least significant bit 37.3.2 SPI control register 2 (SPIx_C2)
Page 664: Spi Baud Rate Register (Spix_Br)
Memory Map and Register Descriptions SPI0_C2 field descriptions (continued) Field Description Bidirectional mode output enable BIDIROE When bidirectional mode is enabled, because SPI pin control 0 (SPC0) is set to 1, the BIDIROE bit determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin.
Page 665: Spi Status Register (Spix_S)
Chapter 37 Serial Peripheral Interface (SPI) SPI0_BR field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 SPI baud rate prescale divisor SPPR[2:0] This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is the bus rate clock (BUSCLK).
Page 666: Freescale Semiconductor, Inc
Memory Map and Register Descriptions SPI0_S field descriptions Field Description SPI read buffer full flag SPRF SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data (D) register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF while it is set and then reading the SPI data register.
Page 667: Spi Data Register (Spix_D)
Chapter 37 Serial Peripheral Interface (SPI) 37.3.5 SPI data register (SPIx_D) This register is both the input and output register for SPI data. A write to the register writes to the transmit data buffer, allowing data to be queued and transmitted. When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately after the previous transmission has completed.
Page 668: Spi Match Register (Spix_M)
Functional Description 37.3.6 SPI match register (SPIx_M) This register contains the hardware compare value. When the value received in the SPI receive data buffer equals this hardware compare value, the SPI match flag (SPMF) sets. Address: 4007_6000h base + 7h offset = 4007_6007h Read Bits[7:0] Write...
Page 669: Master Mode
Chapter 37 Serial Peripheral Interface (SPI) The clock phase control bit (CPHA) and clock polarity control bit (CPOL) in the SPI Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges.
Page 670: Slave Mode
Functional Description mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPIx_S). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data Register in the master occurs, there is a half SPSCK-cycle delay.
Page 671: Spi Transmission By Dma
Chapter 37 Serial Peripheral Interface (SPI) Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. Note When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line.
Page 672: Freescale Semiconductor, Inc
Functional Description RESET Configure DMA Controller for SPI Transmission Configure SPI before Transmission Set TXDMAE/RXDMAE=1 to enable Transmit/Receive by DMA Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave moe Wait for interrupt(s) of DMA Controller indicating end of SPI transmission Figure 37-21.
Page 673: Spi Clock Formats
Chapter 37 Serial Peripheral Interface (SPI) RESET Configure DMA Controller for SPI transmission Configure SPI before Transmission Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave mode Read SPI status register Write the first byte to SPI data register via CPU Set TXDMAE to enable Transmit by Wait for interrupt(s) of DMA Controller...
Page 674: Freescale Semiconductor, Inc
Functional Description The following figure shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the eighth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE.
Page 675: Freescale Semiconductor, Inc
Chapter 37 Serial Peripheral Interface (SPI) of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively.
Page 676: Spi Baud Rate Generation
Functional Description BIT TIME # (REFERENCE) SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) BIT 6 BIT 2 BIT 0 MSB FIRST BIT 7 BIT 1 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7...
Page 677: Special Features
Chapter 37 Serial Peripheral Interface (SPI) The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease I current. The baud rate divisor equation is as follows (except those reserved combinations in the SPI Baud Rate Divisor table).
Page 678: Freescale Semiconductor, Inc
Functional Description 37.4.7.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see the following table). In this mode, the SPI uses only one serial data pin for the interface with one or more external devices.
Page 679: Error Conditions
Chapter 37 Serial Peripheral Interface (SPI) 37.4.8 Error Conditions The SPI module has one error condition: the mode fault error. 37.4.8.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SPSCK lines simultaneously.
Page 680: Freescale Semiconductor, Inc
Functional Description 37.4.9.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode. •...
Page 681: Reset
Chapter 37 Serial Peripheral Interface (SPI) 37.4.9.3 SPI in Stop Mode Operation in a stop mode where the peripheral bus clock is stopped but internal logic states are retained depends on the SPI system. The stop mode does not depend on the SPISWAI bit.
Page 682: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional Description service routine (ISR) should check the flag bits to determine which event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 37.4.11.1 MODF MODF occurs when the master detects an error on the SS pin.
Page 683: Initialization/Application Information
Chapter 37 Serial Peripheral Interface (SPI) 37.4.11.5 Asynchronous interrupt in low power modes When the CPU is in wait mode or stop mode and the SPI module receives a transmission, the SPI module can generate an asynchronous interrupt to wake the CPU from the low power mode.
Page 684: Pseudo-Code Example
Initialization/Application Information 5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data register (SPIx_D) to begin transfer. 37.5.2 Pseudo-Code Example In this example, the SPI module is set up for master mode with only hardware match interrupts enabled.
Page 685: Freescale Semiconductor, Inc
Chapter 37 Serial Peripheral Interface (SPI) SPIx_S = 0x00(%00000000) Bit 5 SPTEF Flag is set when transmit data buffer is empty Bit 4 MODF Mode fault flag for master mode Bit 3:0 Reserved SPIx_M = 0xXX Holds bits 0–7 of the hardware match buffer. SPIx_D = 0xxx Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
Page 686: Freescale Semiconductor, Inc
Initialization/Application Information RESET INITIALIZE SPI SPIxC1 = 0x54 0x80 SPIxC2 = SPIxBR = 0x00 SPTEF = 1 WRITE TO SPIxD SPRF = 1 READ SPIxD SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 37-26.
Page 687: Introduction
Chapter 38 Inter-Integrated Circuit (I2C) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The inter-integrated circuit (I C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing.
Page 688: Modes Of Operation
Introduction • 10-bit address extension • Support for System Management Bus (SMBus) Specification, version 2 • Programmable glitch input filter • Low power mode wakeup on slave address match • Range slave address support • DMA support 38.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: •...
Page 689: Memory Map And Register Descriptions
Chapter 38 Inter-Integrated Circuit (I2C) Module Enable Address Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync In/Out START Data STOP Shift Arbitration Register Control Clock Address Control Compare Figure 38-1. I2C Functional block diagram 38.2 I C signal descriptions The signal properties of I C are shown in the following table.
Page 690: I2C Address Register 1 (I2Cx_A1)
Memory map and register descriptions I2C memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_6000 I2C Address Register 1 (I2C0_A1) 38.3.1/690 4006_6001 I2C Frequency Divider register (I2C0_F) 38.3.2/691 4006_6002 I2C Control Register 1 (I2C0_C1) 38.3.3/692 4006_6003 I2C Status register (I2C0_S)
Page 691: I2C Frequency Divider Register (I2Cx_F)
Chapter 38 Inter-Integrated Circuit (I2C) I2Cx_A1 field descriptions Field Description 7–1 Address AD[7:1] Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme. This field is reserved.
Page 692: I2C Control Register 1 (I2Cx_C1)
Memory map and register descriptions I2Cx_F field descriptions (continued) Field Description Hold times (μs) MULT SCL Start SCL Stop 3.500 3.000 5.500 2.500 4.000 5.250 2.250 4.000 5.250 2.125 4.250 5.125 1.125 4.750 5.125 38.3.3 I2C Control Register 1 (I2Cx_C1) Address: Base address + 2h offset Read IICEN...
Page 693: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description Selects the direction of master and slave transfers. In master mode this bit must be set according to the type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register.
Page 694: I2C Status Register (I2Cx_S)
Memory map and register descriptions 38.3.4 I2C Status register (I2Cx_S) Address: Base address + 3h offset Read BUSY ARBL IICIF RXAK IAAS Write Reset I2Cx_S field descriptions Field Description Transfer Complete Flag This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or immediately following a transfer to or from the I2C module.
Page 695: I2C Data I/O Register (I2Cx_D)
Chapter 38 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description • Any nonzero calling address is received that matches the address in the RA register. • The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers. NOTE: For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
Page 696: I2C Control Register 2 (I2Cx_C2)
Memory map and register descriptions I2Cx_D field descriptions Field Description 7–0 Data DATA In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Page 697: I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
Chapter 38 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions (continued) Field Description Normal drive mode High drive mode Slave Baud Rate Control SBRC Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40 kbps but the slave can capture the master's data at only 10 kbps.
Page 698: I2C Range Address Register (I2Cx_Ra)
Memory map and register descriptions I2Cx_FLT field descriptions (continued) Field Description If the SHEN bit is set to 1 and the I2C module is in an idle or disabled state when the MCU signals to enter stop mode, the module immediately acknowledges the request to enter stop mode. If SHEN is cleared to 0 and the overall data transmission or reception that was suspended by stop mode entry was incomplete: To resume the overall transmission or reception after the MCU exits stop mode, software must reinitialize the transfer by resending the address of the slave.
Page 699: I2C Smbus Control And Status Register (I2Cx_Smb)
Chapter 38 Inter-Integrated Circuit (I2C) I2Cx_RA field descriptions (continued) Field Description This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register. This register's use is similar to that of the A1 register, but in addition this register can be considered a maximum boundary in range matching mode.
Page 700: Freescale Semiconductor, Inc
Memory map and register descriptions I2Cx_SMB field descriptions (continued) Field Description SMBus alert response address matching is disabled SMBus alert response address matching is enabled Second I2C Address Enable SIICAEN Enables or disables SMBus device default address. I2C address register 2 matching is disabled I2C address register 2 matching is enabled Timeout Counter Clock Select TCKSEL...
Page 701: I2C Address Register 2 (I2Cx_A2)
Chapter 38 Inter-Integrated Circuit (I2C) 38.3.10 I2C Address Register 2 (I2Cx_A2) Address: Base address + 9h offset Read Write Reset I2Cx_A2 field descriptions Field Description 7–1 SMBus Address Contains the slave address used by the SMBus. This field is used on the device default address or other related addresses.
Page 702: Functional Description
Functional description 38.4 Functional description This section provides a comprehensive functional description of the I2C module. 38.4.1 I2C protocol The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors.
Page 703: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) 38.4.1.1 START signal The bus is free when no master device is engaging the bus (both SCL and SDA are high). When the bus is free, a master may initiate communication by sending a START signal. A START signal is defined as a high-to-low transition of SDA while SCL is high.
Page 704: Freescale Semiconductor, Inc
Functional description If the slave receiver does not acknowledge the master in the ninth bit, the slave must leave SDA high. The master interprets the failed acknowledgement as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets it as an end to data transfer and releases the SDA line.
Page 705: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of arbitration. 38.4.1.7 Clock synchronization Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects all devices connected on the bus.
Page 706: Freescale Semiconductor, Inc
Functional description 38.4.1.9 Clock stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master drives SCL low, a slave can drive SCL low for the required period and then release it. If the slave's SCL low period is greater than the master's SCL low period, the resulting SCL bus signal's low period is stretched.
Page 707: Bit Address
Chapter 38 Inter-Integrated Circuit (I2C) Table 38-41. I2C divider and hold values (continued) SDA hold SCL hold SCL hold SDA hold SCL hold SCL hold divider value (start) (stop) divider (clocks) (start) (stop) (hex) (hex) value value (clocks) value value 1152 1280 1536...
Page 708: Freescale Semiconductor, Inc
Functional description Table 38-42. Master-transmitter addresses slave-receiver with a 10-bit address Slave Slave Data Data address address first 7 bits second 11110 + byte AD10 + AD[8:1] After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an I2C interrupt.
Page 709: Address Matching
Chapter 38 Inter-Integrated Circuit (I2C) 38.4.3 Address matching All received addresses can be requested in 7-bit or 10-bit address format. • AD[7:1] in Address Register 1, which contains the I2C primary slave address, always participates in the address matching process. It provides a 7-bit address. •...
Page 710: Kl25 Sub-Family Reference Manual, Rev. 3, September
Functional description SDA float high) when it detects any single clock held low longer than T TIMEOUT,MIN Devices that have detected this condition must reset their communication and be able to receive a new START condition within the timeframe of T TIMEOUT,MAX SMBus defines a clock low timeout, T , of 35 ms, specifies T...
Page 711: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) 38.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT The following figure illustrates the definition of the timeout intervals T LOW:SEXT . When in master mode, the I2C module must not cumulatively extend its LOW:MEXT clock cycles for a period greater than T within a byte, where each byte is LOW:MEXT defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP.
Page 712: Resets
Functional description receiving the eighth SCL (8th bit) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent to the bus by setting or clearing the TXAK bit if the FACK (fast ACK/NACK enable) bit is enabled. SMBus requires a device always to acknowledge its own address, as a mechanism to detect the presence of a removable device (such as a battery or docking station) on the bus.
Page 713: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) Table 38-44. Interrupt summary Interrupt source Status Flag Local enable Complete 1-byte transfer IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE C bus stop detection STOPF IICIF IICIE & STOPIE SMBus SCL low timeout SLTF IICIF...
Page 714: Programmable Input Glitch Filter
Functional description 38.4.6.5 Arbitration lost interrupt The I2C is a true multimaster bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure.
Page 715: Address Matching Wakeup
Chapter 38 Inter-Integrated Circuit (I2C) occurs within the number of clock cycles programmed in this register is ignored by the I2C module. The programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. SCL, SDA Noise internal signals...
Page 716: Dma Support
Initialization/application information 38.4.9 DMA support If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an interrupt request. If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMA request instead. DMA requests are generated by the transfer complete flag (TCF).
Page 717: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) 6. Write: Control Register 1 to enable MST (master mode) 7. Write: Data register with the address of the target slave (the LSB of this byte determines whether the communication is master receive or transmit) The routine shown in the following figure encompasses both master and slave I2C operations.
Page 718: Freescale Semiconductor, Inc
Initialization/application information Clear IICIF Master mode? Arbitration Tx/Rx? lost? Last byte Clear ARBL transmitted? Last byte RXAK=0? IIAAS=1? IIAAS=1? to be read? Data transfer see note 2 Address transfer see note 1 End of 2nd to (read) address cycle last byte to be SRW=1? Tx/Rx? (master Rx)?
Page 719: Freescale Semiconductor, Inc
Chapter 38 Inter-Integrated Circuit (I2C) See typical I2C SLTF or FACK=1? interrupt routine SHTF2=1? flow chart Clear IICIF Master mode? Arbitration Tx/Rx? lost? Last byte Last byte Clear ARBL transmitted? to be read? 2nd to RXAK=0? last byte to be IAAS=1? IAAS=1? read?
Page 720: Freescale Semiconductor, Inc
Initialization/application information KL25 Sub-Family Reference Manual, Rev. 3, September 2012 Freescale Semiconductor, Inc.
Page 721: Introduction
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) 39.1 Introduction 39.1.1 Features Features of the UART module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Transmit and receive baud rate can operate asynchronous to the bus clock: •...
Page 722: Modes Of Operation
Introduction 39.1.2 Modes of operation 39.1.2.1 Stop mode The UART will remain functional during Stop mode, provided the asynchronous transmit and receive clock remains enabled. The UART can generate an interrupt or DMA request to cause a wakeup from Stop mode. 39.1.2.2 Wait mode The UART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
Page 723: Freescale Semiconductor, Inc
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) Internal Bus (Write-Only) LOOPS UART_D – Tx Buffer RSRC Loop To Receive 11-BIT Transmit Shift Register Control Data In To TxD Pin Baud Rate Clock SHIFT DIRECTION TXINV Parity Generation UART Controls TxD TO TxD Transmit Control Pin Logic TxD Direction...
Page 724: Register Definition
Register definition INTERNAL BUS SBR12:0 DATA BUFFER BAUDRATE BAUD VARIABLE 12-BIT RECEIVE CLOCK GENERATOR SHIFT REGISTER LBKDE RECEIVE MSBF CONTROL RXINV SHIFT DIRECTION LOOPS RECEIVER RSRC SOURCE CONTROL PARITY WAKEUP LOGIC LOGIC From Transmitter DMA Requests IRQ / DMA ACTIVE EDGE LOGIC IRQ Requests DETECT...
Page 725: Uart Baud Rate Register High (Uartx_Bdh)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UART memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_A005 UART Status Register 2 (UART0_S2) 39.2.6/731 4006_A006 UART Control Register 3 (UART0_C3) 39.2.7/733 4006_A007 UART Data Register (UART0_D) 39.2.8/734 4006_A008 UART Match Address Registers 1 (UART0_MA1)
Page 726: Uart Baud Rate Register Low (Uartx_Bdl)
Register definition UARTx_BDH field descriptions (continued) Field Description 4–0 Baud Rate Modulo Divisor. The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR). 39.2.2 UART Baud Rate Register Low (UARTx_BDL) This register, along with UART _BDH, control the prescale divisor for UART baud rate generation.
Page 727: Freescale Semiconductor, Inc
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C1 field descriptions Field Description Loop Mode Select LOOPS Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input. Normal operation - UART _RX and UART _TX use separate pins. Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
Page 728: Uart Control Register 2 (Uartx_C2)
Register definition 39.2.4 UART Control Register 2 (UARTx_C2) This register can be read or written at any time. Address: Base address + 3h offset Read TCIE ILIE Write Reset UARTx_C2 field descriptions Field Description Transmit Interrupt Enable for TDRE Hardware interrupts from TDRE disabled; use polling. Hardware interrupt requested when TDRE flag is 1.
Page 729: Uart Status Register 1 (Uartx_S1)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C2 field descriptions (continued) Field Description This bit can be written to 1 to place the UART receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is an idle line between messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE = 1, address-mark wakeup.
Page 730: Freescale Semiconductor, Inc
Register definition UARTx_S1 field descriptions (continued) Field Description Receive Data Register Full Flag RDRF RDRF becomes set whenever the receive data buffer is full. To clear RDRF, read the UART data register ( UART _D). Receive data buffer empty. Receive data buffer full. Idle Line Flag IDLE IDLE is set when the UART receive line becomes idle for a full character time after a period of activity.
Page 731: Uart Status Register 2 (Uartx_S2)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_S1 field descriptions (continued) Field Description No parity error. Parity error. 39.2.6 UART Status Register 2 (UARTx_S2) This register contains one read-only status flag. When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time.
Page 732: Freescale Semiconductor, Inc
Register definition UARTx_S2 field descriptions (continued) Field Description LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10].
Page 733: Uart Control Register 3 (Uartx_C3)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) 39.2.7 UART Control Register 3 (UARTx_C3) Address: Base address + 6h offset Read R8T9 R9T8 TXDIR TXINV ORIE NEIE FEIE PEIE Write Reset UARTx_C3 field descriptions Field Description Receive Bit 8 / Transmit Bit 9 R8T9 When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register.
Page 734: Uart Data Register (Uartx_D)
Register definition UARTx_C3 field descriptions (continued) Field Description OR interrupts disabled; use polling. Hardware interrupt requested when OR is set. Noise Error Interrupt Enable NEIE This bit enables the noise flag (NF) to generate hardware interrupt requests. NF interrupts disabled; use polling. Hardware interrupt requested when NF is set.
Page 735: Uart Match Address Registers 1 (Uartx_Ma1)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_D field descriptions (continued) Field Description Read receive data buffer 4 or write transmit data buffer 4. R4T4 Read receive data buffer 3 or write transmit data buffer 3. R3T3 Read receive data buffer 2 or write transmit data buffer 2. R2T2 Read receive data buffer 1 or write transmit data buffer 1.
Page 736: Uart Match Address Registers 2 (Uartx_Ma2)
Register definition 39.2.10 UART Match Address Registers 2 (UARTx_MA2) The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded.
Page 737: Uart Control Register 5 (Uartx_C5)
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C4 field descriptions (continued) Field Description 10-bit Mode select The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when the transmitter and receiver are both disabled. Receiver and transmitter use 8-bit or 9-bit data characters.
Page 738: Functional Description
Functional description UARTx_C5 field descriptions (continued) Field Description Receiver samples input data using the rising edge of the baud rate clock. Receiver samples input data using the rising and falling edge of the baud rate clock. Resynchronization Disable RESYNCDIS When set, disables the resynchronization of the received data word when a data one followed by data zero transition is detected.
Page 739: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) The transmitter output (UART_TX) idle state defaults to logic high, C3[TXINV] is cleared following reset. The transmitter output is inverted by setting C3[TXINV]. The transmitter is enabled by setting the C2[TE] bit. This queues a preamble character that is one full character frame of the idle state.
Page 740: Receiver Functional Description
Functional description the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish whileUART_C2[TE] is cleared, the UART transmitter never actually releases control of the UART_TX pin.
Page 741: Freescale Semiconductor, Inc
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) status flag is set and the new data is lost. Because the UART receiver is double-buffered, the program has one full character time after UART_S1[RDRF] is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D.
Page 742: Freescale Semiconductor, Inc
Functional description In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. 39.3.3.2 Receiver wakeup operation Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver.
Page 743: Additional Uart Functions
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) 39.3.3.2.2 Address-mark wakeup When wake is set, the receiver is configured for address-mark wakeup. In this mode, UART_C2[RWU] is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character. Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames.
Page 744: Freescale Semiconductor, Inc
Functional description 39.3.4.1 8-bit, 9-bit and 10-bit data modes The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting the UART_C1[M] or 10-bit data mode by setting UART_C4[M10]. In 9- bit mode, there is a ninth data bit to the left of the msb of the UART data register, in 10- bit mode there is a tenth data bit.
Page 745: Interrupts And Status Flags
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0) In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on the UART_TX pin. When UART_C3[TXDIR] is cleared, the UART_TX pin is an input to the UART receiver and the transmitter is temporarily disconnected from the UART_TX pin so an external device can send serial data to the receiver.
Page 746: Freescale Semiconductor, Inc
Functional description If the associated error was detected in the received character that caused UART_S1[RDRF] to be set, the error flags - noise flag (UART_S1[NF]), framing error (UART_S1[FE]), and parity error flag (UART_S1[PF]) - are set at the same time as UART_S1[RDRF].
Page 747: Introduction
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) 40.1 Introduction 40.1.1 Features Features of UART module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: •...
Page 748: Modes Of Operation
Introduction 40.1.2 Modes of operation See Section Functional description for details concerning UART operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode 40.1.3 Block diagram The following figure shows the transmitter portion of the UART. INTERNAL BUS MODULE ÷...
Page 749: Freescale Semiconductor, Inc
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) INTERNAL BUS SBR12–SBR0 UART DATA REGISTER (UART_D) MODULE BAUD DIVIDER CLOCK 11-BIT RECEIVE SHIFT REGISTER DATA RECOVERY SHIFT DIRECTION FROM LBKDE TRANSMITTER LOOPS SINGLE-WIRE WAKE WAKEUP LOOP CONTROL RSRC RWUID LOGIC From RxD Pin RXINV RDRF IDLE...
Page 750: Register Definition
Register definition 40.2 Register definition The UART has 8-bit registers to control baud rate, select UART options, report UART status, select DMA options, and for transmit/receive data. Refer to the direct-page register summary in the memory chapter of this document or the absolute address assignments for all UART registers.
Page 751: Uart Baud Rate Register: High (Uartx_Bdh)
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) 40.2.1 UART Baud Rate Register: High (UARTx_BDH) This register, along with UART_BDL, controls the prescale divisor for UART baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to UART_BDH to buffer the high half of the new value and then write to UART_BDL.
Page 752: Uart Control Register 1 (Uartx_C1)
Register definition UART_BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled; that is, UART_C2[RE] or UART_C2[TE] bits are written to 1. Address: Base address + h offset Read Write Reset...
Page 753: Uart Control Register 2 (Uartx_C2)
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) UARTx_C1 field descriptions (continued) Field Description This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output.
Page 754: Freescale Semiconductor, Inc
Register definition UARTx_C2 field descriptions Field Description Transmit Interrupt Enable for TDRE Hardware interrupts from TDRE disabled; use polling. Hardware interrupt requested when TDRE flag is 1. Transmission Complete Interrupt Enable for TC TCIE Hardware interrupts from TC disabled; use polling. Hardware interrupt requested when TC flag is 1.
Page 755: Uart Status Register 1 (Uartx_S1)
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) UARTx_C2 field descriptions (continued) Field Description Normal transmitter operation. Queue break character(s) to be sent. 40.2.5 UART Status Register 1 (UARTx_S1) This register has eight read-only status flags. Writes have no effect. Special software sequences, which do not involve writing to this register, clear these status flags.
Page 756: Uart Status Register 2 (Uartx_S2)
Register definition UARTx_S1 field descriptions (continued) Field Description all 1s, these bit times and the stop bits time count toward the full character time of logic high, 10 or 11 bit times depending on the M control bit, needed for the receiver to detect an idle line. When ILT is set, the receiver doesn't start counting idle bit times until after the stop bits.
Page 757: Freescale Semiconductor, Inc
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master.
Page 758: Uart Control Register 3 (Uartx_C3)
Register definition UARTx_S2 field descriptions (continued) Field Description BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
Page 759: Freescale Semiconductor, Inc
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) UARTx_C3 field descriptions (continued) Field Description such as when it is used to generate mark or space parity, it need not be written each time UART_D is written. TxD Pin Direction in Single-Wire Mode TXDIR When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
Page 760: Uart Data Register (Uartx_D)
Register definition 40.2.8 UART Data Register (UARTx_D) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the UART status flags.
Page 761: Functional Description
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) UARTx_C4 field descriptions Field Description Transmitter DMA Select TDMAS TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt or DMA requests if TIE is set. NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted when the TDRE flag is set, regardless of the state of TDMAS.
Page 762: Baud Rate Generation
Functional description 40.3.1 Baud rate generation As shown in the following figure, the clock source for the UART baud rate generator is the bus-rate clock. Modulo Divide By (1 through 8191) Divide By Tx Baud Rate UART Module Clock SBR[12:0] Rx Sampling Clock Baud Rate Generator (16 ×...
Page 763: Freescale Semiconductor, Inc
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) cleared, UART_BDH[SBNS] is also cleared, selecting the normal 8-bit data mode. In 8- bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new UART character, the value waiting in the transmit data register is transferred to the shift register, synchronized with the baud rate clock, and the transmit data register empty (UART_S1[TDRE]) status flag is set to...
Page 764: Receiver Functional Description
Functional description The length of the break character is affected by the UART_S2[BRK13] and UART_C1[M] bits as shown below. Table 40-31. Break character length BRK13 SBNS Break character length 10 bit times 11 bit times 11 bit times 12 bit times 13 bit times 14 bit times 14 bit times...
Page 765: Freescale Semiconductor, Inc
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) 40.3.3.1 Data sampling technique The UART receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin.
Page 766: Freescale Semiconductor, Inc
Functional description 40.3.3.2 Receiver wakeup operation Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up control bit(UART_C2[RWU]).
Page 767: Interrupts And Status Flags
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames. The one, or two, if UART_BDH[SBNS] = 1, logic 1s msb of an address frame clears the UART_C2[RWU] bit before the stop bits are received and sets the UART_S1[RDRF] flag.
Page 768: Dma Operation
Functional description The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time. IDLE is cleared by reading UARTxS1 while UART_S1[IDLE] is set and then reading UART_D. After UART_S1[IDLE] has been cleared, it cannot become set again until the receiver has received at least one new character and has set UART_S1[RDRF].
Page 769: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2) 40.3.6 Additional UART functions The following sections describe additional UART functions. 40.3.6.1 8- and 9-bit data modes The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting the UART_C1[M]. In 9-bit mode, there is a ninth data bit to the left of the msb of the UART data register.
Page 770: Freescale Semiconductor, Inc
Functional description external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the UART, so it reverts to a general-purpose port I/O pin. 40.3.6.4 Single-wire operation When UART_C1[LOOPS] is set, the RSRC bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1).
Page 771: Introduction
Chapter 41 General-Purpose Input/Output (GPIO) 41.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The general-purpose input and output (GPIO) module communicates to the processor core via a zero wait state interface for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
Page 772: Modes Of Operation
Introduction 41.1.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. Table 41-1. Modes of operation Modes of operation Description The GPIO module operates normally. Wait The GPIO module operates normally. Stop The GPIO module is disabled.
Page 773: Memory Map And Register Definition
Chapter 41 General-Purpose Input/Output (GPIO) 41.1.3.1 Detailed signal description Table 41-3. GPIO interface-detailed signal descriptions Signal Description PORTA31–PORTA0 General-purpose input/output State meaning Asserted: The pin is logic 1. PORTB31–PORTB0 Deasserted: The pin is logic 0. PORTC31–PORTC0 Timing Assertion: When output, this PORTD31–PORTD0 signal occurs on the rising- PORTE31–PORTE0...
Page 774: Freescale Semiconductor, Inc
Memory map and register definition GPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400F_F008 Port Clear Output Register (GPIOA_PCOR) (always 0000_0000h 41.2.3/776 reads 0) 400F_F00C Port Toggle Output Register (GPIOA_PTOR) (always 0000_0000h 41.2.4/777 reads 0)
Page 775: Port Data Output Register (Gpiox_Pdor)
Chapter 41 General-Purpose Input/Output (GPIO) GPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400F_F100 Port Data Output Register (GPIOE_PDOR) 0000_0000h 41.2.1/775 400F_F104 Port Set Output Register (GPIOE_PSOR) (always 0000_0000h 41.2.2/776 reads 0) 400F_F108 Port Clear Output Register (GPIOE_PCOR) (always...
Page 776: Port Set Output Register (Gpiox_Psor)
Memory map and register definition 41.2.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset GPIOx_PSOR field descriptions Field Description 31–0 Port Set Output PTSO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 777: Port Toggle Output Register (Gpiox_Ptor)
Chapter 41 General-Purpose Input/Output (GPIO) 41.2.4 Port Toggle Output Register (GPIOx_PTOR) Address: Base address + Ch offset PTTO Reset GPIOx_PTOR field descriptions Field Description 31–0 Port Toggle Output PTTO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 778: Port Data Direction Register (Gpiox_Pddr)
FGPIO memory map and register definition 41.2.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Reset GPIOx_PDDR field descriptions Field Description 31–0 Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function.
Page 779: Freescale Semiconductor, Inc
Chapter 41 General-Purpose Input/Output (GPIO) FGPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F80F_F008 Port Clear Output Register (FGPIOA_PCOR) (always 0000_0000h 41.3.3/781 reads 0) F80F_F00C Port Toggle Output Register (FGPIOA_PTOR) (always 0000_0000h 41.3.4/782 reads 0)
Page 780: Port Data Output Register (Fgpiox_Pdor)
FGPIO memory map and register definition FGPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F80F_F100 Port Data Output Register (FGPIOE_PDOR) 0000_0000h 41.3.1/780 F80F_F104 Port Set Output Register (FGPIOE_PSOR) (always 0000_0000h 41.3.2/781 reads 0) F80F_F108 Port Clear Output Register (FGPIOE_PCOR) (always...
Page 781: Port Set Output Register (Fgpiox_Psor)
Chapter 41 General-Purpose Input/Output (GPIO) 41.3.2 Port Set Output Register (FGPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset FGPIOx_PSOR field descriptions Field Description 31–0 Port Set Output PTSO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 782: Port Toggle Output Register (Fgpiox_Ptor)
FGPIO memory map and register definition 41.3.4 Port Toggle Output Register (FGPIOx_PTOR) Address: Base address + Ch offset PTTO Reset FGPIOx_PTOR field descriptions Field Description 31–0 Port Toggle Output PTTO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 783: Port Data Direction Register (Fgpiox_Pddr)
Chapter 41 General-Purpose Input/Output (GPIO) 41.3.6 Port Data Direction Register (FGPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Reset FGPIOx_PDDR field descriptions Field Description 31–0 Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function.
Page 784: Ioport
Functional description To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin data clear, and pin data toggle registers exist to allow one or more outputs within one port to be set, cleared, or toggled from a single register write. The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers.
Page 785: Introduction
Chapter 42 Touch Sensing Input (TSI) 42.1 Introduction The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement by a current source scan, charging and discharging the electrode, once or several times.
Page 786: Kl25 Sub-Family Reference Manual, Rev. 3, September
Introduction 42.1.2 Modes of operation This module supports the following operation modes. Table 42-1. Operating modes Mode Description Stop and low power stop TSI module is fully functional in all of the stop modes as long as TSI_GENCS[STPE] is set. The channel specified by TSI_DATA[TSICH] will be scanned upon the trigger.
Page 787: External Signal Description
Chapter 42 Touch Sensing Input (TSI) 42.2 External signal description The TSI module contains up to 16 external pins for touch sensing. The following table describes each of the TSI external pins. Table 42-2. TSI signal description Name Port Direction Function Reset state TSI[15:0]...
Page 788: Freescale Semiconductor, Inc
Register definition NOTE When TSI is working, the configuration bits (GENCS[TSIEN], GENCS[TSIIEN], and GENCS[STM]) must not be changed. The EOSF flag is kept until the software acknowledge it. Address: 4004_5000h base + 0h offset = 4004_5000h MODE REFCHRG DVOLT EXTCHRG Reset NSCN STPE STM...
Page 789: Freescale Semiconductor, Inc
Chapter 42 Touch Sensing Input (TSI) TSIx_GENCS field descriptions (continued) Field Description 27–24 TSI analog modes setup and status bits. MODE Set up TSI analog modes, especially, setting MODE[3:2] to not 2'b00 will configure TSI to noise detection modes. MODE[1:0] take no effect on TSI operation mode and should always write to 2'b00 for setting up. When reading this field will return the analog status.
Page 790: Freescale Semiconductor, Inc
Register definition TSIx_GENCS field descriptions (continued) Field Description Electrode Oscillator Frequency divided by 4 Electrode Oscillator Frequency divided by 8 Electrode Oscillator Frequency divided by 16 Electrode Oscillator Frequency divided by 32 Electrode Oscillator Frequency divided by 64 Electrode Oscillator Frequency divided by 128 12–8 NSCN NSCN...
Page 791: Freescale Semiconductor, Inc
Chapter 42 Touch Sensing Input (TSI) TSIx_GENCS field descriptions (continued) Field Description TSI module disabled. TSI module enabled. Touch Sensing Input Interrupt Enable TSIIEN This bit enables TSI module interrupt request to CPU when the scan completes. The interrupt will wake MCU from low power mode if this interrupt is enabled.
Page 792: Tsi Data Register (Tsix_Data)
Register definition 42.3.2 TSI DATA Register (TSIx_DATA ) Address: 4004_5000h base + 4h offset = 4004_5004h TSICH Reset TSICNT Reset TSIx_DATA field descriptions Field Description 31–28 TSICH TSICH These bits specify current channel to be measured. In hardware trigger mode (TSI_GENCS[STM] = 1), the scan will not start until the hardware trigger occurs.
Page 793: Tsi Threshold Register (Tsix_Tshd)
Chapter 42 Touch Sensing Input (TSI) TSIx_DATA field descriptions (continued) Field Description 1110 Channel 14. 1111 Channel 15. 27–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DMA Transfer Enabled DMAEN This bit is used together with the TSI interrupt enable bits(TSIIE, ESOR) to generate a DMA transfer request instead of an interrupt.
Page 794: Capacitance Measurement
Functional description 42.4.1 Capacitance measurement The electrode pin capacitance measurement uses a dual oscillator approach. The frequency of the TSI electrode oscillator depends on the external electrode capacitance and the TSI module configuration. After going to a configurable prescaler, the TSI electrode oscillator signal goes to the input of the module counter.
Page 795: Freescale Semiconductor, Inc
Chapter 42 Touch Sensing Input (TSI) Electrode Capacitor Charging and Electrode Discharging with constant current Voltage Hysteresis Voltage Delta Time Figure 42-9. TSI electrode oscillator chart The oscillator frequency is give by the following equation * ΔV elec 2 * C elec Figure 42-10.
Page 796: Freescale Semiconductor, Inc
Functional description The pin capacitance sampling time is given by the time the module counter takes to go from zero to its maximum value, defined by NSCN. The electrode sample time is expressed by the following equation: PS * NSCN cap_samp elec Using Equation 1.
Page 797: Tsi Measurement Result
Chapter 42 Touch Sensing Input (TSI) : Internal reference capacitor : Reference oscillator current source ∆V : Hysteresis delta voltage Considering C = 1.0 pF, I = 12 µA and ∆V = 600 mV, follows 12µA 10.0MHz ref_osc 2 *1.0pF * 600mV 42.4.2 TSI measurement result The capacitance measurement result is defined by the number of TSI reference oscillator periods during the sample time and is stored in the TSICHnCNT register.
Page 798: Scan Times
Functional description 42.4.5 Scan times The TSI provides multi-scan function. The number of scans is indicated by the TSI_GENCS[NSCN] bits that allow the scan number from 1 to 32. When TSI_GENCS[NSCN] is set to 0 (only once), the single scan is engaged. The 16-bit counter accumulates all scan results until the NSCN time scan completes, and users can read TSI_DATA[TSICNT] to get this accumulation.
Page 799: Current Source
Chapter 42 Touch Sensing Input (TSI) 42.4.8 Current source The TSI module supports eight different current source power to increment from 500 nA to 64uA. The TSI_GENCS[EXTCHRG] bits determine the current of electrode oscillator that charges and discharges external electrodes. The TSI_GENCS[REFCHRG] bits determine the current of reference oscillator on which the internal reference clock depends.
Page 800: Wake Up Mcu From Low Power Modes
Functional description there is a considerable capacitance change defined by the TSI_TSHD. For instance, if in low power mode the electrode capacitance does not vary, the out-of-range interrupt does not interrupt the CPU. This interrupt will not happen in noise detection mode. It is worthy to note that when the counter value reaches 0xFFFF is treated as an extreme case the out- of-range will not happen.
Page 801: Kl25 Sub-Family Reference Manual, Rev. 3, September
Chapter 42 Touch Sensing Input (TSI) The vmid voltage is defined as V(vmid) = (V(vp) + V(vm))/2. The Rs value is defined by i_ext_3v<2:0> register bits. Figure 42-15. TSI circuit in noise detection mode To determine the noise level the below algorithm can be used: 1.
Page 802: Freescale Semiconductor, Inc
Functional description One example of noise detection mode is shown in the following figure. in this figure the TSI is working in capacitive mode until 30uS when it is changed to noise detection mode. In noise detection mode the selected pad is biased with 0.815V and all AC waveform in this pad is caused by a noise source external to IC.
Page 803: Freescale Semiconductor, Inc
Chapter 42 Touch Sensing Input (TSI) 42.4.13.1 Automatic noise mode This mode is set by MODE[3:2] = 11 (noise mode 3). In this mode, the thresholds are incremented internally by the module until the point that there is no noise voltage trepassing the threshold.
Page 804: Freescale Semiconductor, Inc
Functional description Table 42-12. Signal properties in automatic noise operation mode (continued) Name Function I/O type Power Up/Reset state EXTCHRG[2:1] In this operation mode these bits select the number of filter bits. 00 - 3 filter bits 01 - 2 filter bits 10 - 1 filter bit 11 - no filter bit EXTCHRG[0]...
Page 805: Freescale Semiconductor, Inc
Chapter 42 Touch Sensing Input (TSI) Table 42-13. Signal properties in single noise modes (1,2) (continued) Name Function I/O type Power up / reset DVOLT[1:0], In this operation mode these 4 bits are used select the noise XXXX EXTCHRG[2:1] threshold. 0000 - DVpm = 0.038 V, Vp = 0.834 V, Vm = 0.796 V 0001 - DVpm = 0.050 V, Vp = 0.830 V, Vm = 0.790 V 0010 - DVpm = 0.066 V, Vp = 0.848 V, Vm = 0.782 V...
Page 806 Appendix A Revision History of this Document This appendix describes corrections to the this reference manual for convenience. Grammatical and formatting changes are not listed here unless the meaning of something changed. Changes between revisions 3 and 2 Table A-1. Changes between revisions 3 and 2 Chapter Description Flash Memory Module...
Page 807: Freescale Semiconductor, Inc
How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied Home Page: copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

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NXP Semiconductors KL25 Series Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Alternate Non-Volatile IRC User Trim Description

Chapter 5

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10

Chapter 12 System Integration Module (SIM)

Chapter 13 System Mode Controller (SMC)

Chapter 14 Power Management Controller (PMC)

Chapter 15 Low-Leakage Wakeup Unit (LLWU)

Chapter 16 Reset Control Module (RCM)

Chapter 17 Bit Manipulation Engine (BME)

Chapter 18 Miscellaneous Control Module (MCM)

Chapter 19 Micro Trace Buffer (MTB)

Chapter 20 Crossbar Switch Lite (AXBS-Lite)

Chapter 21 Peripheral Bridge (AIPS-Lite)

Chapter 22 Direct Memory Access Multiplexer (DMAMUX)

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Summary of Contents for NXP Semiconductors KL25 Series