I2C Data I/O Register (I2Cx_D); I2C Control Register 2 (I2Cx_C2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Memory map/register definition

Acknowledge signal was received after the completion of one byte of data transmission on the bus

No acknowledge signal detected

36.4.5 I2C Data I/O register (I2Cx_D)

Address: Base address + 4h offset

In master transmit mode, when data is written to this register, a data transfer is initiated. The most

significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte

NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the

In slave mode, the same functions are available after an address match occurs.

The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the

transmission to begin. For example, if the I2C module is configured for master transmit but a master

receive is desired, reading the Data register does not initiate the receive.

Reading the Data register returns the last byte received while the I2C module is configured in master

receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C

bus, and neither can software verify that a byte has been written to the Data register correctly by reading it

In master transmit mode, the first byte of data written to the Data register following assertion of MST (start

bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the

calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).

Address: Base address + 5h offset

I2Cx_S field descriptions (continued)

I2Cx_D field descriptions

Data register to prevent an inadvertent initiation of a master receive data transfer.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.