Dma Channels With Periodic Triggering Capability - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering
capability
• Channels that implement only the normal routing functionality

20.5.1 DMA channels with periodic triggering capability

Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.
The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration
of the periodic triggering interval is done via configuration registers in the PIT. See the
section on periodic interrupt timer for more information on this topic.
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.
Freescale Semiconductor, Inc.
Note
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 20 Direct Memory Access Multiplexer (DMAMUX)
299