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Module Signal Description Tables
Chip signal name
Module signal
VDDA
VSSA
EXTRG_IN
This table presents the signal descriptions of the CMP0 module.
Chip signal name
Module signal
CMP0_IN[5:0]
CMP0_OUT
This table presents the signal descriptions of the DAC0 module.
Chip signal name
Module signal
DAC0_OUT
Chip signal name
Module signal
VREF_OUT
10.5.5 Timer Modules
Chip signal name
Module signal
TPM_CLKIN[1:0]
TPM_EXTCLK
TPM0_CH[5:0]
120
Table 10-6. ADC0 signal descriptions (continued)
Description
name
V
Analog Power Supply
DDA
V
Analog Ground
SSA
ADHWT
Hardware trigger
Table 10-7. CMP0 signal descriptions
Description
name
IN[5:0]
Analog voltage inputs
CMPO
Comparator output
Table 10-8. DAC0 signal descriptions
Description
name
—
DAC output
Table 10-9. VREF signal descriptions
name
VREF_OUT
Table 10-10. TPM0 signal descriptions
Description
name
External clock. TPM external clock can be selected to increment the
TPM counter on every rising edge synchronized to the counter
clock.
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
Internally-generated voltage reference output
I/O
I
I
I
I/O
I
O
I/O
O
I/O
O
I/O
I
I/O
Freescale Semiconductor, Inc.
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