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The CNR cannot be initialized, but can be read at any time. On each read of the CNR,
software must first write to the CNR with any value. This will synchronize and register
the current value of the CNR into a temporary register. The contents of the temporary
register are returned on each read of the CNR.
When reading the CNR, the bus clock must be at least two times faster than the rate at
which the LPTMR counter is incrementing, otherwise incorrect data may be returned.
31.5.6 LPTMR hardware trigger
The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be
used to trigger hardware events in other peripherals without software intervention. The
hardware trigger is always enabled.
The CMR is set to 0 with CSR[TFC] clear
The CMR is set to a nonzero value, or, if CSR[TFC] is set
31.5.7 LPTMR interrupt
The LPTMR interrupt is generated whenever CSR[TIE] and CSR[TCF] are set.
CSR[TCF] is cleared by disabling the LPTMR or by writing a logic 1 to it.
CSR[TIE] can be altered and CSR[TCF] can be cleared while the LPTMR is enabled.
The LPTMR interrupt is generated asynchronously to the system clock and can be used to
generate a wakeup from any low-power mode, including the low-leakage modes,
provided the LPTMR is enabled as a wakeup source.
Freescale Semiconductor, Inc.
When
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 31 Low-Power Timer (LPTMR)
The LPTMR hardware trigger will assert on the first compare
and does not deassert.
The LPTMR hardware trigger will assert on each compare
and deassert on the following increment of the CNR.
Then
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