Uart Data Register (Uartx_D) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and registers
Field
0 Transmit data is not inverted.
1 Transmit data is inverted.
3 Overrun Error Interrupt Enable
ORIE
Enables the overrun error flag, S1[OR], to generate interrupt requests.
0 OR interrupts are disabled.
1 OR interrupt requests are enabled.
2 Noise Error Interrupt Enable
NEIE
Enables the noise flag, S1[NF], to generate interrupt requests.
0 NF interrupt requests are disabled.
1 NF interrupt requests are enabled.
1 Framing Error Interrupt Enable
FEIE
Enables the framing error flag, S1[FE], to generate interrupt requests.
0 FE interrupt requests are disabled.
1 FE interrupt requests are enabled.
0 Parity Error Interrupt Enable
PEIE
Enables the parity error flag, S1[PF], to generate interrupt requests.
0 PF interrupt requests are disabled.
1 PF interrupt requests are enabled.

38.4.8 UART Data Register (UARTx_D)

This register is actually two separate registers. Reads return the contents of the read-only
receive data register and writes go to the write-only transmit data register.
• In 8-bit or 9-bit data format, only UART data register (D)
needs to be accessed to clear the S1[RDRF] bit . The C3
register needs to be read, prior to the D register, only if the
ninth bit of data needs to be captured.
• In the normal 8-bit mode (M bit cleared) if the parity is
enabled, you get seven data bits and one parity bit. That
one parity bit is loaded into the D register. So, for the data
bits, mask off the parity bit from the value you read out of
this register.
• When transmitting in 9-bit data format and using 8-bit
write instructions, write first to transmit bit 8 in UART
control register 3 (C3[T8]), then D. A write to C3[T8]
692
UARTx_C3 field descriptions (continued)
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
Freescale Semiconductor, Inc.