Mdm-Ap Control Register - NXP Semiconductors MKL27Z128VFM4 Reference Manual

DPACC
Data[31:0] A[3:2] RnW
APSEL
Data[31:0]
Decode
AHB Access Port
(AHB-AP)
Bus Matrix

9.3.1 MDM-AP Control Register

Bit Name
0 Flash Mass Erase in Progress
1 Debug Disable
2 Debug Request
Freescale Semiconductor, Inc.
APACC
Data[31:0] A[3:2] RnW
A[7:4] A[3:2] RnW
MDM-AP
S ee Control and S tatus Register
Descriptions
Figure 9-1. MDM AP addressing
Table 9-3. MDM-AP Control register assignments
1
Secure
Y Set to cause mass erase. Cleared by hardware after mass erase
operation completes.
When mass erase is disabled (via MEEN and SEC settings), the erase
request does not occur and the Flash Mass Erase in Progress bit
continues to assert until the next system reset.
N Set to disable debug. Clear to allow debug operation. When set, it
overrides the C_DEBUGEN bit within the DHCSR and force disables
Debug logic.
N Set to force the core to halt.
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
SW-DP
See the ARM Debug Interface v5p1 Supplement.
Generic
Debug Port
(DP)
SELECT[31:24] (APSEL) selects the AP
SELECT[7:4] (APBANKSEL) selects the bank
A[3:2] from the APACC selects the register
within the bank
AHB-AP
SELECT[31:24] = 0x00 selects the AHB-AP
See ARM documentation for further details
MDM-AP
SELECT[31:24] = 0x01 selects the MDM-AP
SELECT[7:4] = 0x0 selects the bank with Status and Ctrl
A[3:2] = 2'b00 selects the Status Register
A[3:2] = 2'b01 selects the Control Register
SELECT[7:4] = 0xF selects the bank with IDR
A[3:2] = 2'b11 selects the IDR Register
(IDR register reads 0x001C_0020)
Description
Chapter 9 Debug
105