Rtc Status Register (Rtc_Sr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Register definition

32.3.6 RTC Status Register (RTC_SR)

Address: 4003_D000h base + 14h offset = 4003_D014h
Bit 31 30 29
R
W
Reset 0 0 0
15 14 13
Bit
R
W
Reset 0 0 0
Field
31–5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Time Counter Enable
TCE
When time counter is disabled the TSR register and TPR register are writeable, but do not increment.
When time counter is enabled the TSR register and TPR register are not writeable, but increment.
0 Time counter is disabled.
1 Time counter is enabled.
3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 Time Alarm Flag
TAF
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is
cleared by writing the TAR register.
0 Time alarm has not occurred.
1 Time alarm has occurred.
1 Time Overflow Flag
TOF
Time overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do not
increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the
time counter is disabled.
0 Time overflow has not occurred.
1 Time overflow has occurred and time counter is read as zero.
0 Time Invalid Flag
TIF
The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as
zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.
0 Time is valid.
1 Time is invalid and time counter is read as zero.
520
28 27 26 25
0 0 0 0
12 11 10 9
0
0 0 0 0
RTC_SR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24 23 22 21
0
0 0 0 0
8 7 6 5
0 0 0 0
Description
20 19 18 17
0 0 0 0
4 3 2 1
0 TAF TOF
TCE
0 0 0 0
Freescale Semiconductor, Inc.
16
0
0
TIF
1