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Feature
Port A
Pin mux at reset
PTA0/PTA3/
PTA4=ALT7;
Others=ALT0
Lock bit
No
Interrupt and DMA
Yes
request
Digital glitch filter
No
1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open
drain when selected.
PTA20 RESET_b's PUE/PUS are not controlled by
PORTA_PCR20's PUE/PUS, but they are tied to pull up
enabled; LPTMR0_ALT1/2/3 's PUE/PUS is tied to disabled.
11.3 Introduction
11.4 Overview
The Port Control and Interrupt (PORT) module provides support for port control, and
external interrupt functions.
Most functions can be configured independently for each pin in the 32-bit port and affect
the pin regardless of its pin muxing state.
There is one instance of the PORT module for each port. Not all pins within each port are
implemented on a specific device.
11.4.1 Features
The PORT module has the following features:
• Pin interrupt on selected pins
• Interrupt flag and enable registers for each pin
• Support for edge sensitive (rising, falling, both) or level sensitive (low, high)
configured per pin
• Support for interrupt or DMA request configured per pin
Freescale Semiconductor, Inc.
Table 11-1. Ports summary (continued)
Port B
ALT0
No
No
No
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 11 Port Control and Interrupts (PORT)
Port C
Port D
ALT0
ALT0
No
No
Yes
Yes
No
No
Port E
ALT0
No
No
No
127
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