I2S/Sai Operation In Low Power Modes - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

The transmitter and receiver can independently select between the bus clock and the

audio master clock to generate the bit clock. The module's Clocking Mode field of the

Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL]

and RCR2[MSEL]) selects the master clock.

The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for this

TCR2[MSEL], RCR2[MSEL]

40.1.3.5 Clock gating and I

The clock to the I

S/SAI module can be gated using a bit in the SIM. To minimize power

consumption, these bits are cleared after any reset, which disables the clock to the

corresponding module. The clock enable bit should be set by software at the beginning of

the module initialization routine to enable the module clock before initialization of any of

S/SAI registers.

S/SAI operation in low power modes

40.1.4.1 Stop and very low power modes

In Stop mode, the SAI transmitter and/or receiver can continue operating provided the

appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively),

and provided the transmitter and/or receiver is/are using an externally generated bit clock

or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter

and/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.

In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered

from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might

underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth.

In VLPW and VLPR modes, the module is limited by the maximum bus clock

frequencies.

Freescale Semiconductor, Inc.

Table 40-2. I2S0 master clock settings

S/SAI initialization

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 40 Synchronous Audio Interface (SAI)

Master Clock

Not supported