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Chapter 40
Synchronous Audio Interface (SAI)
40.1 Chip-specific I2S information
40.1.1 Instantiation information
This device contains one I
As configured on the device, module features include:
• TX data lines: 1
• RX data lines: 1
• FIFO size (words): 1
• Maximum words per frame: 2
• Maximum bit clock divider: 512
40.1.2 I2S Interrupts
The I2S0 has receive and transmit sources of interrupt requests. However, these sources
are OR'd together to generate a single interrupt request to the interrupt controller. When
an I2S0 interrupt occurs, read the I2S0_RCSR and I2S0_TCSR to determine the exact
interrupt source.
2
40.1.3 I
S/SAI clocking
Freescale Semiconductor, Inc.
2
S module.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
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