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Memory Map and Registers
Absolute
address
(hex)
Shifter Buffer N Bit Byte Swapped Register
4005_F38C
(FLEXIO_SHIFTBUFBBS3)
4005_F400
Timer Control N Register (FLEXIO_TIMCTL0)
4005_F404
Timer Control N Register (FLEXIO_TIMCTL1)
4005_F408
Timer Control N Register (FLEXIO_TIMCTL2)
4005_F40C Timer Control N Register (FLEXIO_TIMCTL3)
4005_F480
Timer Configuration N Register (FLEXIO_TIMCFG0)
4005_F484
Timer Configuration N Register (FLEXIO_TIMCFG1)
4005_F488
Timer Configuration N Register (FLEXIO_TIMCFG2)
4005_F48C Timer Configuration N Register (FLEXIO_TIMCFG3)
4005_F500
Timer Compare N Register (FLEXIO_TIMCMP0)
4005_F504
Timer Compare N Register (FLEXIO_TIMCMP1)
4005_F508
Timer Compare N Register (FLEXIO_TIMCMP2)
4005_F50C Timer Compare N Register (FLEXIO_TIMCMP3)
39.3.1 Version ID Register (FLEXIO_VERID)
.
Address: 4005_F000h base + 0h offset = 4005_F000h
Bit
31
30
29
28
27
26
MAJOR
R
W
0
0
0
0
0
0
Reset
Field
31–24
Major Version Number
MAJOR
750
FLEXIO memory map (continued)
Register name
25
24
23
22
21
20
19
18
MINOR
0
1
0
0
0
0
0
0
FLEXIO_VERID field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
(in bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
Section/
Access
Reset value
39.3.16/
R/W
0000_0000h
39.3.17/
R/W
0000_0000h
39.3.17/
R/W
0000_0000h
39.3.17/
R/W
0000_0000h
39.3.17/
R/W
0000_0000h
39.3.18/
R/W
0000_0000h
39.3.18/
R/W
0000_0000h
39.3.18/
R/W
0000_0000h
39.3.18/
R/W
0000_0000h
39.3.19/
R/W
0000_0000h
39.3.19/
R/W
0000_0000h
39.3.19/
R/W
0000_0000h
39.3.19/
R/W
0000_0000h
9
8
7
6
5
4
3
FEATURE
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
page
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764
764
766
766
766
766
2
1
0
0
0
0
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