Sopt1 Configuration Register (Sim_Sopt1Cfg) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition
Field
19–18 32K Oscillator Clock Select
OSC32KSEL
Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This field is reset only on POR/LVD.
00 System oscillator (OSC32KCLK)
01 Reserved
10 RTC_CLKIN
11 LPO 1kHz
17–16 32K oscillator clock output
OSC32KOUT
Outputs the ERCLK32K on the selected pin in all modes of operation (including LLS/VLLS and System
Reset), overriding the existing pin mux configuration for that pin. This field is reset only on POR/LVD.
00 ERCLK32K is not output.
01 ERCLK32K is output on PTE0.
10 ERCLK32K is output on PTE26.
11 Reserved.
15–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
Reserved This field is reserved.

12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)

The SOPT1CFG register is reset on System Reset not VLLS.
Address: 4004_7000h base + 4h offset = 4004_7004h
Bit 31 30 29
0
R
W
Reset 0 0 0
Bit 15 14 13
R
W
Reset
0 0 0
146
SIM_SOPT1 field descriptions (continued)
NOTE
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
24 23 22 21
0 0 0 0
8 7 6 5
0
0 0 0 0
20 19 18 17
0
0 0 0 0
4 3 2 1
0 0 0 0
Freescale Semiconductor, Inc.
16
0
0
0