Spi Clear Interrupt Register (Spix_Ci) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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35.4.9 SPI clear interrupt register (SPIx_CI)

This register applies only for an instance of the SPI module that supports the FIFO

The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits

clears the corresponding interrupts if the INTCLR bit in the C3 register is 1. Reading

these bits always returns 0.

This register also has two read-only bits to indicate the transmit FIFO and receive FIFO

overrun conditions. When the receive FIFO is full and data is received, RXFOF is set.

Similarily, when the transmit FIFO is full and a write to the data register occurs, TXFOF

is set. These flags are cleared when the CI register is read while the flags are set.

The register has two more read-only bits to indicate the error flags. These flags are set

when, due to some spurious reason, entries in the FIFO total more than 64 bits of data. At

this point, all the flags in the status register are reset, and entries in the FIFO are flushed

with the corresponding error flags set. These flags are cleared when the CI register is read

while the flags are set.

Address: Base address + Ah offset

Transmit FIFO error flag

This flag indicates that a transmit FIFO error occurred because entries in the FIFO total more than 64 bits

No transmit FIFO error occurred

A transmit FIFO error occurred

Receive FIFO error flag

This flag indicates that a receive FIFO error occurred because entries in the FIFO total more than 64 bits

No receive FIFO error occurred

A receive FIFO error occurred

Transmit FIFO overflow flag

This flag indicates that a transmit FIFO overflow condition has occurred.

Freescale Semiconductor, Inc.

SPIx_CI field descriptions

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 35 Serial Peripheral Interface (SPI)