System Reset Status Register 1 (Rcm_Srs1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
5 Watchdog
WDOG
Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by
disabling the watchdog.
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Low-Voltage Detect Reset
LVD
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
0 Low Leakage Wakeup Reset
WAKEUP
Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a
low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any
enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except
WAKEUP.
0 Reset not caused by LLWU module wakeup source
1 Reset caused by LLWU module wakeup source

22.2.2 System Reset Status Register 1 (RCM_SRS1)

This register includes read-only status flags to indicate the source of the most recent
reset. The reset state of these bits depends on what caused the MCU to reset.
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x00
• LVD (without POR) — 0x00
• VLLS mode wakeup — 0x00
• Other reset — a bit is set if its corresponding reset source
caused the reset
Freescale Semiconductor, Inc.
RCM_SRS0 field descriptions (continued)
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 22 Reset Control Module (RCM)
Description
327