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Internal voltage regulator
26.3.2.3 SC[MODE_LV] = 10
The internal VREF bandgap is on. The low power buffer is enabled to generate a buffered
1.2 V voltage to VREF_OUT. It can also be used as a reference to internal analog
peripherals such as an ADC channel or analog comparator input.
If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1)
there will be a delay before the buffer output is settled at the final value. This is the buffer
start up delay (Tstup) and the value is specified in the appropriate device data sheet. If
this mode is entered when the VREF module is enabled then you must wait the longer of
Tstup or until SC[VREFST] = 1 when the chop oscillator is not enabled. If the chop
oscillator is being used, you must wait the time specified by Tchop_osc_stup (chop
oscillator start up time) to ensure the VREF output has stabilized.
In this mode, a 100 nF capacitor is required to connect between the VREF_OUT pin and
VSSA.
26.3.2.4 SC[MODE_LV] = 11
Reserved
26.4 Internal voltage regulator
The VREF module contains an internal voltage regulator that can be enabled to provide
additional supply noise rejection. It is recommended that when possible, this regulator be
enabled to provide the optimum VREF performance.
1. Enable the chop oscillator (VREF_TRM[CHOPEN] = 1)
2. Configure the VREF_SC register to the desired settings with the internal regulator
disabled, VREF_SC[REGEN] = 0
3. Wait > 300ns
4. Enable the internal regulator by setting VREF_SC[REGEN] to 1
26.5 Initialization/Application Information
The Voltage Reference requires some time for startup and stabilization. After
SC[VREFEN] = 1, SC[VREFST] can be monitored to determine if the stabilization and
startup is completed when the chop oscillator is not enabled. When the chop oscillator is
enabled, the settling time of the internal bandgap reference is defined by Tchop_osc_stup
430
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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