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11.7.1 Pin Control Register n (PORTx_PCRn)
See the Signal Multiplexing and Pin Assignment chapter for the
reset value of this device.
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
not available in your selected package. All unbonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Address: Base address + 0h offset + (4d × i), where i=0d to 31d
Bit
31
30
29
R
W
Reset
0
0
0
15
14
13
Bit
0
R
W
Reset
0
0
0
* Notes:
•
MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
•
DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port.
•
PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
•
SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
•
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
•
PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
Field
31–25
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
24
Interrupt Status Flag
ISF
This field is read-only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes.
Freescale Semiconductor, Inc.
NOTE
28
27
26
25
0
0
0
0
0
12
11
10
9
MUX
0
0
*
*
PORTx_PCRn field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 11 Port Control and Interrupts (PORT)
24
23
22
21
ISF
0
w1c
0
0
0
0
8
7
6
5
0
0
DSE
*
0
*
0
Description
20
19
18
17
IRQC
0
0
0
0
4
3
2
1
0
PFE
SRE
PE
*
0
*
*
16
0
0
PS
*
135
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