Functional Description; Clock Domains - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description

Field
00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture
events are also ignored.
11 TPM counter continues in debug mode.
5 Doze Enable
DOZEEN
Configures the TPM behavior in wait mode.
0 Internal TPM counter continues in Doze mode.
1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input
capture events are also ignored.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
29.5 Functional description
The following sections describe the TPM features.

29.5.1 Clock domains

The TPM module supports two clock domains.
The bus clock domain is used by the register interface and for synchronizing interrupts
and DMA requests.
The TPM counter clock domain is used to clock the counter and prescaler along with the
output compare and input capture logic. The TPM counter clock is considered
asynchronous to the bus clock, can be a higher or lower frequency than the bus clock and
can remain operational in Stop mode. Multiple TPM instances are all clocked by the
same TPM counter clock in support of the external timebase feature.
29.5.1.1 Counter Clock Mode
The CMOD[1:0] bits in the SC register either disable the TPM counter or select one of
two possible clock modes for the TPM counter. After any reset, CMOD[1:0] = 0:0 so the
TPM counter is disabled.
The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter by
writing zero to the CMOD[1:0] bits does not affect the TPM counter value or other
registers, but must be acknowledged by the TPM counter clock domain before they read
as zero.
474
TPMx_CONF field descriptions (continued)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
Freescale Semiconductor, Inc.