Baud Rate Generation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Functional description

Match address operation functions in the same way for both MA1 and MA2 registers.

Note that the position of the address mark is the same as the Parity Bit when parity is

enabled for 8 bit and 9 bit data formats.

• If only one of C4[MAEN1] and C4[MAEN2] is asserted, a marked address is

compared only with the associated match register and data is transferred to the

receive data buffer only on a match.

• If C4[MAEN1] and C4[MAEN2] are asserted, a marked address is compared with

both match registers and data is transferred only on a match with either register.

Address match operation is not supported when C7816[ISO_7816E] is set/enabled.

38.5.3 Baud rate generation

A 13-bit modulus counter and a 5-bit fractional fine-adjust counter in the baud rate

generator derive the baud rate for both the receiver and the transmitter. The value from 1

to 8191 written to SBR[12:0] determines the module clock divisor. The SBR bits are in

the UART baud rate registers, BDH and BDL. The baud rate clock is synchronized with

the module clock and drives the receiver. The fractional fine-adjust counter adds

fractional delays to the baud rate clock to allow fine trimming of the baud rate to match

the system baud rate. The transmitter is driven by the baud rate clock divided by 16. The

receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to two sources of error:

• Integer division of the module clock may not give the exact target frequency. This

error can be reduced with the fine-adjust counter.

• Synchronization with the module clock can cause phase shift.

lists the available baud divisor fine adjust values.

UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD))

The following table lists some examples of achieving target baud rates with a module

clock frequency of 10.2 MHz, with and without fractional fine adjustment.

Table 38-8. Baud rates (example: module clock = 10.2 MHz)

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.